時序錯誤
Overview
| Works: | 4 works in 0 publications in 0 languages | |
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Titles
容忍時序錯誤的管線積體電路設計 = = Design of Pipelined VLSI Circuits for Tolerating Timing Errors /
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容忍多重時序錯誤之管線化電路設計 = = Design of Pipelined Circuits for Tolerating Multiple Timing Errors /
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容忍時序錯誤之彈性管線設計 = = Design of Elastic Pipelines for Tolerating Timing Errors /
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可復原時序錯誤之管線的時序延遲填補 = = Delay Padding for Timing-Error-Resilient Pipelines /
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