晶片網路
概要
| 作品: | 19 作品在 3 項出版品 3 種語言 | |
|---|---|---|
書目資訊
鏈結動態電壓調整之低功率晶片網路的設計與評估 = = Design and Evaluation of a Low-Power On-Chip Network Based on Dynamic Voltage Scaling with Links /
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晶片網路功率消耗管理之動態頻率調整技術設計 = = Design of Dynamic Frequency-Scaling Technique for Managing Power Consumption in NoC /
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適用於晶片網路中之多功混合式通訊交換器設計 = = A Versatile Hybrid Switch Architecture for On-Chip Networks /
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基於樹狀尋徑架構之晶片網路交換器 = = A Switch for Tree-Based Routing Architectures in On-Chip Networks /
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用於電路交換晶片網路之高效率排程 = = Efficient Switch scheduling for Circuit-Switched On-Chip Networks /
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應用於非同步電路連接同步核心交換器之晶片網路設計 = = Asynchronous Circuits Interconnect By Using Synchronous Core Switch For NoC Applications /
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電路交換晶片網路之排程的設計與評估 = = Design and Evaluation of Scheduling for Circuit-Switched Network-on-Chip Architectures /
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晶片網路架構之容錯尋徑設計與評估 = = Design and Evaluation of Fault-Tolerant Routing for Network-on-Chip Architectures /
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不規則網格晶片網路之樹狀繞徑 = = Tree-Based Routing for On-Chip Networks with Irregular Mesh Topology /
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具大矽核心二維格狀晶片網路之繞徑樹的有效建構 = = Effective construction of routing trees for 2D mesh on-chip networks with over-size IP cores /
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尋找有缺陷二維晶片網路之有效樹狀繞徑 = = Searching for efficient tree-based routing in faulty 2D mesh on-chip networks /
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晶片網路功率消耗管理之適應性動態調整技術 = = Design of Dynamic Adaptive Technique for Managing Power Consumption in NoCs /
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電路交換晶片網路之映對與排程 = = Efficient Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures /
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系統晶片設計上之晶片網路的設計與評估 = = Design and evaluation of network-on-chip architectures for SoC design /
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具有錯誤元件之晶片網路架構的尋徑設計 = = Routing for Network-on-Chip Architectures with Faulty Components /
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