東華大學圖書館 |

語系: 繁體中文

說明(常見問題)

回圖書館首頁

手機版館藏查詢

登入

回首頁 到查詢結果 [ subject:"Interconnects (Integrated circuit technology)" ]

切換: 標籤 | MARC模式 | ISBD

Multi-net optimization of VLSI inter...

Moiseev, Konstantin.

FindBook

Google Book

Amazon

博客來

Multi-net optimization of VLSI interconnect

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Multi-net optimization of VLSI interconnect/ by Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer.
作者:	Moiseev, Konstantin.
其他作者:	Kolodny, Avinoam.
出版者:	New York, NY :Springer New York : : 2015.,
面頁冊數:	xvi, 233 p. :ill. (some col.), digital ;24 cm.
內容註:	An Overview of the VLSI Interconnect Problem -- Interconnect Aspects in Design Methodology and EDA Tools -- Scaling Dependent Electrical Modeling of Interconnects -- Net-by-Net Wire Optimization -- Multi-Net Sizing and Spacing of Bundle Wires -- Multi-net Sizing and Spacing in General Layouts -- Interconnect Optimization by Net Ordering -- Layout Migration -- Future Directions in Interconnect Optimization.
Contained By:	Springer eBooks
標題:	Interconnects (Integrated circuit technology) -
電子資源:	http://dx.doi.org/10.1007/978-1-4614-0821-5
ISBN:	9781461408215 (electronic bk.)

Multi-net optimization of VLSI interconnect
Moiseev, Konstantin.

Multi-net optimization of VLSI interconnect[electronic resource] /by Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. - New York, NY :Springer New York :2015. - xvi, 233 p. :ill. (some col.), digital ;24 cm.

An Overview of the VLSI Interconnect Problem -- Interconnect Aspects in Design Methodology and EDA Tools -- Scaling Dependent Electrical Modeling of Interconnects -- Net-by-Net Wire Optimization -- Multi-Net Sizing and Spacing of Bundle Wires -- Multi-net Sizing and Spacing in General Layouts -- Interconnect Optimization by Net Ordering -- Layout Migration -- Future Directions in Interconnect Optimization.

ISBN: 9781461408215 (electronic bk.)

Standard No.: 10.1007/978-1-4614-0821-5doiSubjects--Topical Terms:

831881
Interconnects (Integrated circuit technology)

LC Class. No.: TK7874.53

Dewey Class. No.: 621.3815

Multi-net optimization of VLSI interconnect
LDR:01361nmm a2200301 a 4500 001 1993528
003 DE-He213
005 20150714091058.0
006 m d
007 cr nn 008maaau
008 151019s2015 nyu s 0 eng d
020 $a 9781461408215 (electronic bk.)
020 $a 9781461408208 (paper)
024 7 $a 10.1007/978-1-4614-0821-5 $2 doi
035 $a 978-1-4614-0821-5
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7874.53
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 621.3815 $2 23
090 $a TK7874.53 $b .M714 2015
100 1 $a Moiseev, Konstantin. $3 2131831
245 1 0 $a Multi-net optimization of VLSI interconnect $h [electronic resource] / $c by Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer.
260 $a New York, NY : $b Springer New York : $b Imprint: Springer, $c 2015.
300 $a xvi, 233 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a An Overview of the VLSI Interconnect Problem -- Interconnect Aspects in Design Methodology and EDA Tools -- Scaling Dependent Electrical Modeling of Interconnects -- Net-by-Net Wire Optimization -- Multi-Net Sizing and Spacing of Bundle Wires -- Multi-net Sizing and Spacing in General Layouts -- Interconnect Optimization by Net Ordering -- Layout Migration -- Future Directions in Interconnect Optimization.
650 0 $a Interconnects (Integrated circuit technology) $3 831881
650 0 $a Integrated circuits $x Very large scale integration. $3 535389
650 1 4 $a Engineering. $3 586835
650 2 4 $a Circuits and Systems. $3 896527
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 893838
650 2 4 $a Processor Architectures. $3 892680
700 1 $a Kolodny, Avinoam. $3 2131832
700 1 $a Wimer, Shmuel. $3 2131833
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-1-4614-0821-5
950 $a Engineering (Springer-11647)