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Efficient execution of irregular dat...

Shah, Nimish.

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Efficient execution of irregular dataflow graphs = hardware/software co-optimization for probabilistic AI and sparse linear algebra /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Efficient execution of irregular dataflow graphs/ by Nimish Shah, Wannes Meert, Marian Verhelst.
其他題名:	hardware/software co-optimization for probabilistic AI and sparse linear algebra /
作者:	Shah, Nimish.
其他作者:	Meert, Wannes.
出版者:	Cham :Springer Nature Switzerland : : 2023.,
面頁冊數:	xxi, 143 p. :ill., digital ;24 cm.
內容註:	Chapter 1. Irregular workloads at risk of losing the hardware lottery -- Chapter 2. Suitable data representation: A study of fixed point, floating point,and positTM formats for probabilistic AI -- Chapter 3. GraphOpt: constrained-optimization-based parallelization of irregular workloads for multicore processors -- Chapter 4. DAG Processing Unit version 1 (DPU): Efficient execution of irregular workloads on a multicore processor -- Chapter 5. DAG Processing Unit version 2 (DPU-v2): Efficient execution of irregular workloads on a spatial datapath -- Chapter 6. Conclusions and future work.
Contained By:	Springer Nature eBook
標題:	Electronic circuits - Data processing. -
電子資源:	https://doi.org/10.1007/978-3-031-33136-7
ISBN:	9783031331367

Efficient execution of irregular dataflow graphs = hardware/software co-optimization for probabilistic AI and sparse linear algebra /
Shah, Nimish.

Efficient execution of irregular dataflow graphshardware/software co-optimization for probabilistic AI and sparse linear algebra /[electronic resource] :by Nimish Shah, Wannes Meert, Marian Verhelst. - Cham :Springer Nature Switzerland :2023. - xxi, 143 p. :ill., digital ;24 cm.

Chapter 1. Irregular workloads at risk of losing the hardware lottery -- Chapter 2. Suitable data representation: A study of fixed point, floating point,and positTM formats for probabilistic AI -- Chapter 3. GraphOpt: constrained-optimization-based parallelization of irregular workloads for multicore processors -- Chapter 4. DAG Processing Unit version 1 (DPU): Efficient execution of irregular workloads on a multicore processor -- Chapter 5. DAG Processing Unit version 2 (DPU-v2): Efficient execution of irregular workloads on a spatial datapath -- Chapter 6. Conclusions and future work.

This book focuses on the acceleration of emerging irregular sparse workloads, posed by novel artificial intelligent (AI) models and sparse linear algebra. Specifically, the book outlines several co-optimized hardware-software solutions for a highly promising class of emerging sparse AI models called Probabilistic Circuit (PC) and a similar sparse matrix workload for triangular linear systems (SpTRSV) The authors describe optimizations for the entire stack, targeting applications, compilation, hardware architecture and silicon implementation, resulting in orders of magnitude higher performance and energy-efficiency compared to the existing state-of-the-art solutions. Thus, this book provides important building blocks for the upcoming generation of edge AI platforms. Analyzes the key bottlenecks in the existing platforms for these sparse and irregular AI and linear algebra algorithms; Discusses an emerging set of AI workloads that rely on sparse matrix operations and graph-based computations; Shows how to address the execution challenges of this novel class of algorithms through hardware-software codesign.

ISBN: 9783031331367

Standard No.: 10.1007/978-3-031-33136-7doiSubjects--Topical Terms:

880697
Electronic circuits
--Data processing.

LC Class. No.: TK7867 / .S53 2023

Dewey Class. No.: 621.3815028563

Efficient execution of irregular dataflow graphs = hardware/software co-optimization for probabilistic AI and sparse linear algebra /
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520 $a This book focuses on the acceleration of emerging irregular sparse workloads, posed by novel artificial intelligent (AI) models and sparse linear algebra. Specifically, the book outlines several co-optimized hardware-software solutions for a highly promising class of emerging sparse AI models called Probabilistic Circuit (PC) and a similar sparse matrix workload for triangular linear systems (SpTRSV) The authors describe optimizations for the entire stack, targeting applications, compilation, hardware architecture and silicon implementation, resulting in orders of magnitude higher performance and energy-efficiency compared to the existing state-of-the-art solutions. Thus, this book provides important building blocks for the upcoming generation of edge AI platforms. Analyzes the key bottlenecks in the existing platforms for these sparse and irregular AI and linear algebra algorithms; Discusses an emerging set of AI workloads that rely on sparse matrix operations and graph-based computations; Shows how to address the execution challenges of this novel class of algorithms through hardware-software codesign.
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