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Automated analysis of virtual protot...

Goli, Mehran.

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Automated analysis of virtual prototypes at the electronic system level = design understanding and applications /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Automated analysis of virtual prototypes at the electronic system level/ by Mehran Goli, Rolf Drechsler.
其他題名:	design understanding and applications /
作者:	Goli, Mehran.
其他作者:	Drechsler, Rolf.
出版者:	Cham :Springer International Publishing : : 2020.,
面頁冊數:	xxi, 166 p. :ill., digital ;24 cm.
內容註:	Chapter 1. Introduction -- Chapter 2. Background -- Chapter 3. Design Understanding Methodology -- Chapter 4. Application I: Verification -- Chapter 5. Application II: Security Validation -- Chapter 6. Application III: Design Space Exploration -- Chapter 7. Conclusion.
Contained By:	Springer eBooks
標題:	Prototypes, Engineering. -
電子資源:	https://doi.org/10.1007/978-3-030-44282-8
ISBN:	9783030442828

Automated analysis of virtual prototypes at the electronic system level = design understanding and applications /
Goli, Mehran.

Automated analysis of virtual prototypes at the electronic system leveldesign understanding and applications /[electronic resource] :by Mehran Goli, Rolf Drechsler. - Cham :Springer International Publishing :2020. - xxi, 166 p. :ill., digital ;24 cm.

Chapter 1. Introduction -- Chapter 2. Background -- Chapter 3. Design Understanding Methodology -- Chapter 4. Application I: Verification -- Chapter 5. Application II: Security Validation -- Chapter 6. Application III: Design Space Exploration -- Chapter 7. Conclusion.

This book describes a set of SystemC-based virtual prototype analysis methodologies, including design understanding, verification, security validation, and design space exploration. Readers will gain an overview of the latest research results in the field of Electronic Design Automation (EDA) at the Electronic System Level (ESL) The methodologies discussed enable readers to tackle easily key tasks and applications in the design process. Provides an extensive introduction to the field of SystemC-based virtual prototype (VP) analysis at the electronic system level; Describes a design understanding methodology from both debugger-based and compiler-based perspectives; Illustrates a semi-formal verification approach to check the validity of a given VP against its specification, user-defined rules and protocol; Discusses a security validation approach to validate the run-time behavior of a given VP-based SoC against security threat models, such as information leakage (confidentiality) and unauthorized access to data in a memory (integrity); Describes a design space exploration approach for SystemC-based VPs to guide designers to know under which error limits, different portions of a given VP can be approximated at different granularity levels.

ISBN: 9783030442828

Standard No.: 10.1007/978-3-030-44282-8doiSubjects--Topical Terms:

659312
Prototypes, Engineering.

LC Class. No.: TS171.8 / .G655 2020

Dewey Class. No.: 620.0042

Automated analysis of virtual prototypes at the electronic system level = design understanding and applications /
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