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Methodologies for reliable and effic...

Murali, Srinivasan.

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Methodologies for reliable and efficient design of networks on chips.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Methodologies for reliable and efficient design of networks on chips./
作者:	Murali, Srinivasan.
面頁冊數:	249 p.
附註:	Adviser: Giovanni De Micheli.
Contained By:	Dissertation Abstracts International68-02B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3253520

Methodologies for reliable and efficient design of networks on chips.
Murali, Srinivasan.

Methodologies for reliable and efficient design of networks on chips. - 249 p.

Adviser: Giovanni De Micheli.

Thesis (Ph.D.)--Stanford University, 2007.

Thus, the design methodology presented in this thesis bridges an important design gap that exists today, in building efficient communication architectures for MPSoCs.Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Methodologies for reliable and efficient design of networks on chips.
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245 1 0 $a Methodologies for reliable and efficient design of networks on chips.
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500 $a Source: Dissertation Abstracts International, Volume: 68-02, Section: B, page: 1195.
502 $a Thesis (Ph.D.)--Stanford University, 2007.
520 $a Thus, the design methodology presented in this thesis bridges an important design gap that exists today, in building efficient communication architectures for MPSoCs.
520 $a The growing complexity of Multiprocessor Systems on Chips (MPSoCs) is requiring communication resources that can only be provided by a highly-scalable communication infrastructure. This trend is exemplified by the growing number of Networks on Chip (NoC) architectures that are being proposed recently for MPSoC integration. Developing NoC-based systems tailored to a particular application domain is crucial for achieving high-performance, energy-efficient customized solutions. The effectiveness of this approach largely depends on the availability of a design methodology that, starting from a high-level application specification, derives an optimized NoC configuration with respect to different design objectives and instantiates the selected application specific on-chip micro-network. Automatic execution of these design steps is highly desirable to increase SoC design productivity.
520 $a With technology scaling, as the geometries of the transistors reach the physical limits of operation, another important design challenge of SoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. Designing systems under such uncertain conditions becomes a challenge.
520 $a In this thesis, I present novel and state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design, such as topology synthesis, core mapping, crossbar sizing, route generation, resource reservation, achieving fault-tolerance, RTL code and layout generation. The methods are integrated into a complete tool flow, Netchip, for designing reliable and efficient NoCs for application-specific SoCs and chip multi-processors.
520 $a The nature of contributions of this work are of two kinds: scientific and engineering. First, from the scientific viewpoint, novel algorithmic methods are presented to solve many of the important NoC design problems. These methods will be useful for designers to tackle specific problems in NoC design. Second, from the engineering viewpoint, the SoC designer can directly use the tool flow as a black-box to design efficient interconnects and to perform design space exploration of different communication architectures.
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