鏈結動態電壓調整之低功率晶片網路的設計與評估 = = Design a...
張兆宏

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  • 鏈結動態電壓調整之低功率晶片網路的設計與評估 = = Design and Evaluation of a Low-Power On-Chip Network Based on Dynamic Voltage Scaling with Links /
  • Record Type: Language materials, printed : Monograph/item
    Title/Author: 鏈結動態電壓調整之低功率晶片網路的設計與評估 = / 張兆宏撰
    Reminder of title: Design and Evaluation of a Low-Power On-Chip Network Based on Dynamic Voltage Scaling with Links /
    remainder title: Design and Evaluation of a Low-Power On-Chip Network Based on Dynamic Voltage Scaling with Links
    Author: 張兆宏
    Published: [花蓮縣壽豐鄉] : [國立東華大學資訊工程學系], : 民92[2003],
    Description: 8,61面 : 圖,表 ; 30公分
    Notes: 指導教授︰紀新洲
    Subject: 低功率 -
    Online resource: http://134.208.10.124/ETD-db/ETD-search-c/view_etd?URN=etd-0730103-170607PDF全文
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GE0034618 五樓論文區 (5F Theses & Dissertations) 03.不外借_N 本校碩士論文 T 312.9 1133 一般使用(Normal) On shelf 0
  • 1 records • Pages 1 •
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