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Incremental design techniques with n...

Ma, Jing.

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Incremental design techniques with non-preemptive refinement for million-gate FPGAs.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Incremental design techniques with non-preemptive refinement for million-gate FPGAs./
作者:	Ma, Jing.
面頁冊數:	180 p.
附註:	Co-Chairs: Peter M. Athanas; Mark T. Jones.
Contained By:	Dissertation Abstracts International63-11B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3069880
ISBN:	0493896740

Incremental design techniques with non-preemptive refinement for million-gate FPGAs.
Ma, Jing.

Incremental design techniques with non-preemptive refinement for million-gate FPGAs. - 180 p.

Co-Chairs: Peter M. Athanas; Mark T. Jones.

Thesis (Ph.D.)--Virginia Polytechnic Institute and State University, 2003.

This dissertation presents a Field Programmable Gate Array (FPGA) design methodology that can be used to shorten the FPGA design-and-debug cycle, especially as gate counts increase to many millions. Core-based incremental placement algorithms, in conjunction with fast interactive routing, are investigated to reduce the design processing time by distinguishing the changes between design iterations and reprocessing only the changed blocks without affecting the remaining part of the design. Different from other incremental placement algorithms, this tool provides the function not only to handle small modifications; it can also incrementally place a large design from scratch at a rapid rate. Incremental approaches are inherently greedy techniques, but when combined with a background refinement thread, the incremental approach offers the instant gratification that designers expect, while preserving the fidelity attained through batch-oriented programs. An incremental FPGA design tool has been developed, based on the incremental placement algorithm and its background refiner.

ISBN: 0493896740Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Incremental design techniques with non-preemptive refinement for million-gate FPGAs.
LDR:02695nam 2200289 a 45 001 937208
005 20110511
008 110511s2003 eng d
020 $a 0493896740
035 $a (UnM)AAI3069880
035 $a AAI3069880
040 $a UnM $c UnM
100 1 $a Ma, Jing. $3 1261073
245 1 0 $a Incremental design techniques with non-preemptive refinement for million-gate FPGAs.
300 $a 180 p.
500 $a Co-Chairs: Peter M. Athanas; Mark T. Jones.
500 $a Source: Dissertation Abstracts International, Volume: 63-11, Section: B, page: 5416.
502 $a Thesis (Ph.D.)--Virginia Polytechnic Institute and State University, 2003.
520 $a This dissertation presents a Field Programmable Gate Array (FPGA) design methodology that can be used to shorten the FPGA design-and-debug cycle, especially as gate counts increase to many millions. Core-based incremental placement algorithms, in conjunction with fast interactive routing, are investigated to reduce the design processing time by distinguishing the changes between design iterations and reprocessing only the changed blocks without affecting the remaining part of the design. Different from other incremental placement algorithms, this tool provides the function not only to handle small modifications; it can also incrementally place a large design from scratch at a rapid rate. Incremental approaches are inherently greedy techniques, but when combined with a background refinement thread, the incremental approach offers the instant gratification that designers expect, while preserving the fidelity attained through batch-oriented programs. An incremental FPGA design tool has been developed, based on the incremental placement algorithm and its background refiner.
520 $a Design applications with logical gate sizes varying from tens of thousands to approximately one million are built to evaluate the execution of the algorithms and the design tool. The results show that this incremental design tool is two orders of magnitude faster than the competing approaches such as the Xilinx M3 tools without sacrificing much quality. The tool presented places designs at the speed of 700,000 system gates per second. The fast processing speed and user-interactive property make the incremental design tool potentially useful for prototype developing, system debugging and modular testing in million-gate FPGA designs.
590 $a School code: 0247.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 0 $a Virginia Polytechnic Institute and State University. $3 1017496
773 0 $t Dissertation Abstracts International $g 63-11B.
790 $a 0247
790 1 0 $a Athanas, Peter M., $e advisor
790 1 0 $a Jones, Mark T., $e advisor
791 $a Ph.D.
792 $a 2003
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3069880