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The sources and effects of leakage c...

Park, Jae-Eun.

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The sources and effects of leakage currents on nonvolatile memories.

Record Type:	Language materials, printed : Monograph/item
Title/Author:	The sources and effects of leakage currents on nonvolatile memories./
Author:	Park, Jae-Eun.
Description:	86 p.
Notes:	Chair: Dieter Schroder.
Contained By:	Dissertation Abstracts International62-05B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3014562
ISBN:	0493245472

The sources and effects of leakage currents on nonvolatile memories.
Park, Jae-Eun.

The sources and effects of leakage currents on nonvolatile memories. - 86 p.

Chair: Dieter Schroder.

Thesis (Ph.D.)--Arizona State University, 2001.

There are many different types of semiconductor memories. They can be divided into volatile and nonvolatile. Nonvolatile memories (NVM) are distinct from volatile memories in that the information stored is maintained after the power supply is removed. The basic principle of floating gate-based NVMs is shifting the threshold voltage of a metal-oxide-semiconductor field transistor (MOSFET) by charging or discharging a floating gate. Although these NVMs are more flexible and scalable than other nonvolatile memories, inherent “disturb” problems hinder the devices from expanding their market. The main cause for “disturb” originates from memory cell architecture designed for high packing density. Since total cell isolation from other cells is very impractical, it becomes important to solve and minimize the “disturb” issues for NVMs. Any unintentional change of threshold voltage can be considered as a “disturb” which causes erratic logic decisions. In terms of “disturb” origins, the current “disturb” and charge “disturb” are discussed in this dissertation. The pn junction leakage current brings about high charge injection into the floating gate during “writing” and “erasing” operations. Also under low electric fields, small charge compensation can be made by low gate leakage current through the floating gate. This current increases as the gate oxides are stressed after “writing” and “erasing” as well as “reading” operation. These stressed oxides tend to have traps generated by high electric fields, which shift the threshold voltage without compensating charges in the floating gate.

ISBN: 0493245472Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

The sources and effects of leakage currents on nonvolatile memories.
LDR:02896nam 2200277 a 45 001 929567
005 20110427
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020 $a 0493245472
035 $a (UnM)AAI3014562
035 $a AAI3014562
040 $a UnM $c UnM
100 1 $a Park, Jae-Eun. $3 1253056
245 1 0 $a The sources and effects of leakage currents on nonvolatile memories.
300 $a 86 p.
500 $a Chair: Dieter Schroder.
500 $a Source: Dissertation Abstracts International, Volume: 62-05, Section: B, page: 2436.
502 $a Thesis (Ph.D.)--Arizona State University, 2001.
520 $a There are many different types of semiconductor memories. They can be divided into volatile and nonvolatile. Nonvolatile memories (NVM) are distinct from volatile memories in that the information stored is maintained after the power supply is removed. The basic principle of floating gate-based NVMs is shifting the threshold voltage of a metal-oxide-semiconductor field transistor (MOSFET) by charging or discharging a floating gate. Although these NVMs are more flexible and scalable than other nonvolatile memories, inherent “disturb” problems hinder the devices from expanding their market. The main cause for “disturb” originates from memory cell architecture designed for high packing density. Since total cell isolation from other cells is very impractical, it becomes important to solve and minimize the “disturb” issues for NVMs. Any unintentional change of threshold voltage can be considered as a “disturb” which causes erratic logic decisions. In terms of “disturb” origins, the current “disturb” and charge “disturb” are discussed in this dissertation. The pn junction leakage current brings about high charge injection into the floating gate during “writing” and “erasing” operations. Also under low electric fields, small charge compensation can be made by low gate leakage current through the floating gate. This current increases as the gate oxides are stressed after “writing” and “erasing” as well as “reading” operation. These stressed oxides tend to have traps generated by high electric fields, which shift the threshold voltage without compensating charges in the floating gate.
520 $a As the devices are scaled down, “disturb” problems are aggravated due to the increased leakage current, high electric fields and fabrication issues. In this dissertation, this author also discusses NVM fabrication issues, which can induce stress and gate oxide degradations.
590 $a School code: 0010.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 0 $a Arizona State University. $3 1017445
773 0 $t Dissertation Abstracts International $g 62-05B.
790 $a 0010
790 1 0 $a Schroder, Dieter, $e advisor
791 $a Ph.D.
792 $a 2001
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3014562