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Design and modeling of non-classical...

University of California, San Diego., Electrical Engineering (Applied Physics).

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Design and modeling of non-classical MOSFETs.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Design and modeling of non-classical MOSFETs./
Author:	Yu, Bo.
Description:	185 p.
Notes:	Advisers: Yuan Taur; Peter Asbeck.
Contained By:	Dissertation Abstracts International70-09B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3372587
ISBN:	9781109365887

Design and modeling of non-classical MOSFETs.
Yu, Bo.

Design and modeling of non-classical MOSFETs. - 185 p.

Advisers: Yuan Taur; Peter Asbeck.

Thesis (Ph.D.)--University of California, San Diego, 2009.

As bulk CMOS scaling is approaching the limit that is imposed by gate oxide tunneling, body doping, band-to-band tunneling, etc., non-classical MOSFET is becoming an intense subject of very large-scale integration (VLSI) research. Among a variety of non-classical MOSFETs, multiple-gate (MG) MOSFETs which are still based on Si have been proposed to scale down CMOS technology more aggressively because of better control of short-channel effects (SCEs), whereas novel MOSFETs utilizing III-V materials instead of Si are suggested to achieve CMOS performance breakthrough even without scaling down too aggressively due to the large mobility of mobile carriers. This dissertation focuses on the design and modeling of these two categories of non-classical MOSFETs.

ISBN: 9781109365887Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Design and modeling of non-classical MOSFETs.
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020 $a 9781109365887
035 $a (UMI)AAI3372587
035 $a AAI3372587
040 $a UMI $c UMI
100 1 $a Yu, Bo. $3 1044760
245 1 0 $a Design and modeling of non-classical MOSFETs.
300 $a 185 p.
500 $a Advisers: Yuan Taur; Peter Asbeck.
500 $a Source: Dissertation Abstracts International, Volume: 70-09, Section: B, page: .
502 $a Thesis (Ph.D.)--University of California, San Diego, 2009.
520 $a As bulk CMOS scaling is approaching the limit that is imposed by gate oxide tunneling, body doping, band-to-band tunneling, etc., non-classical MOSFET is becoming an intense subject of very large-scale integration (VLSI) research. Among a variety of non-classical MOSFETs, multiple-gate (MG) MOSFETs which are still based on Si have been proposed to scale down CMOS technology more aggressively because of better control of short-channel effects (SCEs), whereas novel MOSFETs utilizing III-V materials instead of Si are suggested to achieve CMOS performance breakthrough even without scaling down too aggressively due to the large mobility of mobile carriers. This dissertation focuses on the design and modeling of these two categories of non-classical MOSFETs.
520 $a Actually, many different types of Si-based MG MOSFETs have been designed and even fabricated in the last two decades, including double-gate (DG) MOSFETs, surrounding-gate (SG) MOSFETs, quadruple-gate (QG) MOSFETs, triple-gate (TG) MOSFETs, pi-gate MOSFETs, O-gate MOSFETs, and so on. Although the design work has been pretty much done, specific compact models for these MG MOSFETs other than BSIM, PSP, and HiSIM are in urgent need, because the charge sheet approximation is no longer appropriate for MG MOSFETs due to the so-called "volume inversion" effect. In this dissertation, we will first introduce the complete non-charge-sheet based analytic models of drain current, terminal charges and capacitance coefficients for long channel symmetric DG and SG MOSFETs. The DG and SG models will be generalized to a unified analytic drain current model for all kinds of MG MOSFETs, with some non-trivial yet reasonable approximations. Efforts will also be focused on making the physics-based model more versatile and computationally efficient.
520 $a On the contrary, the research on III-V MOSFETs is still in the primary phase. Compact modeling for III-V MOSFETs is not being considered in the current stage because the device technology itself is far away from maturity, and the interest of this dissertation is in device design and basic physical modeling. With SCEs treated as the top-drawer consideration, a baseline device design of III-V MOSFET for sub-22nm scaling is proposed based on the thin-BOX-SOI-like structure. Physical modeling of capacitances in III-V MOSFETs has also been carried out to gain a more clear picture of capacitance degradation due to small density-of-states (DOS).
590 $a School code: 0033.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 0 $a University of California, San Diego. $b Electrical Engineering (Applied Physics). $3 1044759
773 0 $t Dissertation Abstracts International $g 70-09B.
790 $a 0033
790 1 0 $a Asbeck, Peter, $e advisor
790 1 0 $a Bandaru, Prabhakar $e committee member
790 1 0 $a Cheng, Chung-Kuan $e committee member
790 1 0 $a Lo, Yuhwa $e committee member
790 1 0 $a Taur, Yuan, $e advisor
791 $a Ph.D.
792 $a 2009
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3372587