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Integrated circuit and system design...

Monteiro, Jose.

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Integrated circuit and system design = power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, revised selected papers/

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Integrated circuit and system design/ Lars Svensson, Jose Monteiro (eds.)
Reminder of title:	power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, revised selected papers/
other author:	Monteiro, Jose.
corporate name:	PATMOS 2008
Published:	Berlin, Heidelberg :Springer Berlin Heidelberg, : 2009.,
Description:	xiii, 462 p. :ill., digital ;24 cm.
Series:	Lecture notes in computer science,
Contained By:	Springer eBooks
Subject:	Integrated circuits - Congresses. - Very large scale integration -
Online resource:	http://dx.doi.org/10.1007/978-3-540-95948-9
ISBN:	9783540959472 (paper)

Integrated circuit and system design = power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, revised selected papers/
Integrated circuit and system designpower and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, revised selected papers/[electronic resource] :Lars Svensson, Jose Monteiro (eds.) - Berlin, Heidelberg :Springer Berlin Heidelberg,2009. - xiii, 462 p. :ill., digital ;24 cm. - Lecture notes in computer science,53490302-9743 ;.

ISBN: 9783540959472 (paper)Subjects--Topical Terms:

893429
Integrated circuits
--Very large scale integration--Congresses.

Dewey Class. No.: 621.395

Integrated circuit and system design = power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, revised selected papers/
LDR:00922nam 2200217 a 45 001 842251
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005 20100602
006 m d
007 cr nn 008maaau
008 100602s2009 gw j eng d
020 $a 9783540959472 (paper)
020 $a 9783540959489 (electronic bk.)
035 $a 978-3-540-95947-2
082 0 4 $a 621.395 $2 22
111 2 $a PATMOS 2008 $d (2008 : $c Lisbon, Portugal) $3 1002172
245 1 0 $a Integrated circuit and system design $h [electronic resource] : $b power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, revised selected papers/ $c Lars Svensson, Jose Monteiro (eds.)
260 $a Berlin, Heidelberg : $c 2009. $b Springer Berlin Heidelberg,
300 $a xiii, 462 p. : $b ill., digital ; $c 24 cm.
440 0 $a Lecture notes in computer science, $x 0302-9743 ; $v 5349
650 0 $a Integrated circuits $x Very large scale integration $x Computer-aided design $v Congresses. $3 893429
650 1 4 $a Computer Science. $3 626642
650 2 4 $a Arithmetic and Logic Structures. $3 893182
650 2 4 $a Circuits and Systems. $3 896527
650 2 4 $a Logic Design. $3 892735
650 2 4 $a Memory Structures. $3 898261
650 2 4 $a Processor Architectures. $3 892680
650 2 4 $a System Performance and Evaluation. $3 891353
700 1 $a Monteiro, Jose. $3 1002170
700 1 $a Svensson, Lars. $3 1002171
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-3-540-95948-9
950 $a Computer Science (Springer-11645; ZDB-2-SCS)