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Reduced instruction set computer arc...
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Katevenis, Manolis G. H.
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Reduced instruction set computer architectures for VLSI /
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
正題名/作者:
Reduced instruction set computer architectures for VLSI // Manolis G.H. Katevenis.
作者:
Katevenis, Manolis G. H.
出版者:
Cambridge, Mass. :MIT Press, : c1985.,
面頁冊數:
215 p. :ill. ;24 cm.
附註:
Includes index.
標題:
Computer architecture. -
ISBN:
0262111039
Reduced instruction set computer architectures for VLSI /
Katevenis, Manolis G. H.
Reduced instruction set computer architectures for VLSI /
Manolis G.H. Katevenis. - Cambridge, Mass. :MIT Press,c1985. - 215 p. :ill. ;24 cm. - ACM doctoral dissertation awards ;1984. - ACM doctoral dissertation award ;1984..
Includes index.
Bibliography: p. [201]-207.
ISBN: 0262111039
LCCN: 85000078 Subjects--Topical Terms:
559837
Computer architecture.
LC Class. No.: QA76.9.A73 / K37 1985
Dewey Class. No.: 621.3819/5835
Reduced instruction set computer architectures for VLSI /
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