東華大學圖書館 |

Language: English

Help

回圖書館首頁

手機版館藏查詢

Back

Switch To: Labeled | MARC Mode | ISBD

Integrated Circuit and System Design...

Paliouras, Vassilis.

Linked to FindBook

Google Book

Amazon

博客來

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : = 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation :/ edited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest.
Reminder of title:	15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings
remainder title:	PATMOS 2005
other author:	Paliouras, Vassilis.
corporate name:	PATMOS 2005
Published:	Berlin Heidelberg :Springer-Verlag GmbH., : 2005.,
Description:	xv, 753 p. :ill., digital ;24 cm.
Series:	Lecture Notes in Computer Science,
Contained By:	Springer e-books
Subject:	Integrated circuits - Congresses. - Very large scale integration -
Online resource:	http://dx.doi.org/10.1007/11556930http://dx.doi.org/10.1007/11556930
ISBN:	9783540290131 (paper)

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : = 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation :15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings[electronic resource]/PATMOS 2005edited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest. - Berlin Heidelberg :Springer-Verlag GmbH.,2005. - xv, 753 p. :ill., digital ;24 cm. - Lecture Notes in Computer Science,37280302-9743 ;.

ISBN: 9783540290131 (paper)Subjects--Topical Terms:

893429
Integrated circuits
--Very large scale integration--Congresses.

LC Class. No.: TK7874.75 / .P38 2005

Dewey Class. No.: 621.3815

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : = 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings
LDR:01059nam a2200253 a 45 001 764683
003 Springer
005 20080716
006 m d
007 cr nn 008maaau
008 080716s2005 gw j eng d
020 $a 9783540290131 (paper)
020 $a 9783540320807 (electronic bk.)
035 $a 978-3-540-29013-1
040 $a NDHU $c NDHU $d NDHU
050 0 0 $a TK7874.75 $b .P38 2005
082 0 0 $a 621.3815 $2 22
111 $a PATMOS 2005 $d (2005 : $c Louvain, Belgium) $3 893428
245 1 0 $a Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : $b 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings $h [electronic resource]/ $c edited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest.
246 3 0 $a PATMOS 2005
260 $a Berlin Heidelberg : $c 2005. $b Springer-Verlag GmbH.,
300 $a xv, 753 p. : $b ill., digital ; $c 24 cm.
440 0 $a Lecture Notes in Computer Science, $x 0302-9743 ; $v 3728
650 $a Integrated circuits $x Very large scale integration $x Computer-aided design $v Congresses. $3 893429
650 $a Computer Science. $3 626642
650 $a Arithmetic and Logic Structures. $3 893182
650 $a Computer-Aided Engineering (CAD, CAE) and Design. $3 892568
650 $a Electronic and Computer Engineering. $3 891119
650 $a Logic Design. $3 892735
650 $a Performance and Reliability. $3 893430
650 $a Processor Architectures. $3 892680
700 $a Paliouras, Vassilis. $3 893425
700 $a Verkest, Diederik. $3 893426
700 $a Vounckx, Johan. $3 893427
710 $a SpringerLink (Online service) $3 836513
773 0 $t Springer e-books
856 4 0 $u http://dx.doi.org/10.1007/11556930 $z http://dx.doi.org/10.1007/11556930
950 $a Computer Science (Springer-11645; ZDB-2-SCS)