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Peripheral Circuit Design Techniques...

Upton, Luke Robert,

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Peripheral Circuit Design Techniques for Emerging Memory /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Peripheral Circuit Design Techniques for Emerging Memory // Luke Robert Upton.
Author:	Upton, Luke Robert,
Description:	1 electronic resource (208 pages)
Notes:	Source: Dissertations Abstracts International, Volume: 86-06, Section: A.
Contained By:	Dissertations Abstracts International86-06A.
Subject:	Random access memory. -
Online resource:	https://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=31757686
ISBN:	9798346786429

Peripheral Circuit Design Techniques for Emerging Memory /
Upton, Luke Robert,

Peripheral Circuit Design Techniques for Emerging Memory /Luke Robert Upton. - 1 electronic resource (208 pages)

Source: Dissertations Abstracts International, Volume: 86-06, Section: A.

As the capabilities of consumer electronics grow, so too does the need for low-energy, low-cost, and process-compatible embedded non-volatile memory (NVM). Resistive RAM (RRAM) is a technology that can meet this NVM need using materials and processes already available in a wide range of CMOS processes. However, (1) the read/write circuits required to access the information stored in a cell are often larger than the RRAM cells themselves in a macro, (2) there are competing pressures of decreasing read latency and increasing average read energy in an RRAM macro, and (3) the information stored in an RRAM cell must be retained even as the cell conductance experiences time-based variation. In this dissertation, we explore design methods for high-density, low energy RRAM storage macros. First, we present modeling approaches for RRAM macro readout circuit latency, energy, and thermal noise - spanning both voltage-based and current-based conductance sense amplifiers. From these models, we investigate the tradeoff between average read energy and input-referred thermal noise and find that there is not an inherent advantage in the voltage-based or current-based sensing scheme across all macro use cases. We then present a method to design small driver and pass gate circuits while providing the current and voltage necessary for RRAM cell write. The readout circuit models and write circuit area models are combined to generate prospective energy-area tradeoff curves for macro designs given RRAM cell parameters. This method allows designers to estimate read energy and macro density limits given an RRAM technology. Next, we demonstrate the Efficient Multiple-Bits-per-Cell Embedded RRAM (EMBER) macro, which uses the aforementioned read and write circuit design models/techniques to achieve a low read energy (1.0 pJ/bit single-bit-per-cell) with small unit cell area (5.6e-3 F2 single-bit-per-cell, F = 40 nm) compared to prior art. We also use experimental data obtained from EMBER to determine conductance level allocations most suitable for fast, low-BER write as well as conductance level allocations most suitable for low-energy, low-BER read over an extended period of time. Finally, we demonstrate that our read/write circuit design approach is not just applicable to RRAM, but to other emerging resistive NVMs as well.

English

ISBN: 9798346786429Subjects--Topical Terms:

623617
Random access memory.

Peripheral Circuit Design Techniques for Emerging Memory /
LDR:03670nmm a22003973i 4500 001 2430660
005 20250527055724.5
006 m o d
007 cr|nu||||||||
008 261011s2024 miu||||||m |||||||eng d
020 $a 9798346786429
035 $a (MiAaPQD)AAI31757686
035 $a (MiAaPQD)Stanforddj427mq8691
035 $a AAI31757686
040 $a MiAaPQD $b eng $c MiAaPQD $e rda
100 1 $a Upton, Luke Robert, $e author. $3 3819090
245 1 0 $a Peripheral Circuit Design Techniques for Emerging Memory / $c Luke Robert Upton.
264 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2024
300 $a 1 electronic resource (208 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Dissertations Abstracts International, Volume: 86-06, Section: A.
500 $a Advisors: Wong, H. S. Philip Committee members: Mitra, Subhasish; Murmann, Boris; Bent, Stacey F.
502 $b Ph.D. $c Stanford University $d 2024.
520 $a As the capabilities of consumer electronics grow, so too does the need for low-energy, low-cost, and process-compatible embedded non-volatile memory (NVM). Resistive RAM (RRAM) is a technology that can meet this NVM need using materials and processes already available in a wide range of CMOS processes. However, (1) the read/write circuits required to access the information stored in a cell are often larger than the RRAM cells themselves in a macro, (2) there are competing pressures of decreasing read latency and increasing average read energy in an RRAM macro, and (3) the information stored in an RRAM cell must be retained even as the cell conductance experiences time-based variation. In this dissertation, we explore design methods for high-density, low energy RRAM storage macros. First, we present modeling approaches for RRAM macro readout circuit latency, energy, and thermal noise - spanning both voltage-based and current-based conductance sense amplifiers. From these models, we investigate the tradeoff between average read energy and input-referred thermal noise and find that there is not an inherent advantage in the voltage-based or current-based sensing scheme across all macro use cases. We then present a method to design small driver and pass gate circuits while providing the current and voltage necessary for RRAM cell write. The readout circuit models and write circuit area models are combined to generate prospective energy-area tradeoff curves for macro designs given RRAM cell parameters. This method allows designers to estimate read energy and macro density limits given an RRAM technology. Next, we demonstrate the Efficient Multiple-Bits-per-Cell Embedded RRAM (EMBER) macro, which uses the aforementioned read and write circuit design models/techniques to achieve a low read energy (1.0 pJ/bit single-bit-per-cell) with small unit cell area (5.6e-3 F2 single-bit-per-cell, F = 40 nm) compared to prior art. We also use experimental data obtained from EMBER to determine conductance level allocations most suitable for fast, low-BER write as well as conductance level allocations most suitable for low-energy, low-BER read over an extended period of time. Finally, we demonstrate that our read/write circuit design approach is not just applicable to RRAM, but to other emerging resistive NVMs as well.
546 $a English
590 $a School code: 0212
650 4 $a Random access memory. $3 623617
650 4 $a Space exploration. $3 3696172
650 4 $a Energy. $3 876794
650 4 $a Macros. $3 3819091
650 4 $a Transistors. $3 713271
650 4 $a Design techniques. $3 3561498
650 4 $a Aerospace engineering. $3 1002622
650 4 $a Computer science. $3 523869
650 4 $a Design. $3 518875
690 $a 0791
690 $a 0538
690 $a 0984
690 $a 0389
710 2 $a Stanford University. $e degree granting institution. $3 3765820
720 1 $a Wong, H. S. Philip $e degree supervisor.
773 0 $t Dissertations Abstracts International $g 86-06A.
790 $a 0212
791 $a Ph.D.
792 $a 2024
856 4 0 $u https://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=31757686