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Top Gate Dielectric Engineering for ...

Ko, Jung-Soo,

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Top Gate Dielectric Engineering for Two-Dimensional Transition Metal Dichalcogenides /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Top Gate Dielectric Engineering for Two-Dimensional Transition Metal Dichalcogenides // Jung-Soo Ko.
Author:	Ko, Jung-Soo,
Description:	1 electronic resource (109 pages)
Notes:	Source: Dissertations Abstracts International, Volume: 86-05, Section: B.
Contained By:	Dissertations Abstracts International86-05B.
Subject:	Aluminum. -
Online resource:	https://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=31652047
ISBN:	9798346380863

Top Gate Dielectric Engineering for Two-Dimensional Transition Metal Dichalcogenides /
Ko, Jung-Soo,

Top Gate Dielectric Engineering for Two-Dimensional Transition Metal Dichalcogenides /Jung-Soo Ko. - 1 electronic resource (109 pages)

Source: Dissertations Abstracts International, Volume: 86-05, Section: B.

Silicon technology scaling is reaching its physical limits, which is triggering the need for alternative materials. Two-dimensional transition metal dichalcogenides (2D TMDs) are promising semiconductors showing good carrier mobility even at sub-nm channel thickness in metal oxide semiconductor (MOS) transistors. However, due to the lack of partially filled dangling bonds, atomic layer deposition (ALD) for ultrathin and highquality gate stacks on top of TMDs does not work well. As a result, fulfilling the technology requirement of sub-1 nm equivalent oxide thickness (EOT) on 2D TMDs has been challenging using industry-compatible materials and processes. In this work, I introduce three approaches to deposit ultrathin top gate dielectrics on 2D TMDs using CMOScompatible materials and processes that achieve 1-nm-scale top gate EOT.First, I investigate depositing ultrathin electron-beam evaporated seed layers that enable nucleation of high-κ dielectric ALD on monolayer MoS2 and WSe2. Several evaporated seed layer candidates (Si, Ge, Hf, Gd, La, Al2O3) are tested, and evaporated Si seed is revealed to work best for monolayer MoS2 transistors without damage and with good interfacial quality. Using Si seed layer followed by ALD of HfO2, top-gated monolayer TMD transistors are demonstrated which achieve top gate EOT of ~0.9 nm and minimum subthreshold swing of 70 mV/dec (at room temperature) with almost no hysteresis observed. This work also uncovers threshold voltage engineering by controlling the seed layer thicknesses.Next, I introduce nanofog aluminum oxide (AlOx) on monolayer MoS2 as the interfacial gate dielectric layer. Coverage of nanofog AlOx on monolayer MoS2 as a function of deposition temperature is studied, which reveals that deposition temperature of 50 °C provides most uniform coverage. Nanofog AlOx is also found to provide a high-quality dielectric interfacial layer on MoS2 compared to other seed layer deposition techniques. MoS2 transistors using nanofog AlOx followed by ALD HfO2 as top gate dielectric show negligible hysteresis and sufficiently good interface trap density that enable subthreshold swing of sub-100 mV/dec at room temperature. By using a bilayer gate dielectric stack of nanofog AlOx and HfO2, MoS2 transistors with 1-nm-scale top gate EOT are demonstrated with low gate leakage and excellent uniformity owing to the nanofog AlOx.

English

ISBN: 9798346380863Subjects--Topical Terms:

735071
Aluminum.

Top Gate Dielectric Engineering for Two-Dimensional Transition Metal Dichalcogenides /
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520 $a Silicon technology scaling is reaching its physical limits, which is triggering the need for alternative materials. Two-dimensional transition metal dichalcogenides (2D TMDs) are promising semiconductors showing good carrier mobility even at sub-nm channel thickness in metal oxide semiconductor (MOS) transistors. However, due to the lack of partially filled dangling bonds, atomic layer deposition (ALD) for ultrathin and highquality gate stacks on top of TMDs does not work well. As a result, fulfilling the technology requirement of sub-1 nm equivalent oxide thickness (EOT) on 2D TMDs has been challenging using industry-compatible materials and processes. In this work, I introduce three approaches to deposit ultrathin top gate dielectrics on 2D TMDs using CMOScompatible materials and processes that achieve 1-nm-scale top gate EOT.First, I investigate depositing ultrathin electron-beam evaporated seed layers that enable nucleation of high-κ dielectric ALD on monolayer MoS2 and WSe2. Several evaporated seed layer candidates (Si, Ge, Hf, Gd, La, Al2O3) are tested, and evaporated Si seed is revealed to work best for monolayer MoS2 transistors without damage and with good interfacial quality. Using Si seed layer followed by ALD of HfO2, top-gated monolayer TMD transistors are demonstrated which achieve top gate EOT of ~0.9 nm and minimum subthreshold swing of 70 mV/dec (at room temperature) with almost no hysteresis observed. This work also uncovers threshold voltage engineering by controlling the seed layer thicknesses.Next, I introduce nanofog aluminum oxide (AlOx) on monolayer MoS2 as the interfacial gate dielectric layer. Coverage of nanofog AlOx on monolayer MoS2 as a function of deposition temperature is studied, which reveals that deposition temperature of 50 °C provides most uniform coverage. Nanofog AlOx is also found to provide a high-quality dielectric interfacial layer on MoS2 compared to other seed layer deposition techniques. MoS2 transistors using nanofog AlOx followed by ALD HfO2 as top gate dielectric show negligible hysteresis and sufficiently good interface trap density that enable subthreshold swing of sub-100 mV/dec at room temperature. By using a bilayer gate dielectric stack of nanofog AlOx and HfO2, MoS2 transistors with 1-nm-scale top gate EOT are demonstrated with low gate leakage and excellent uniformity owing to the nanofog AlOx.
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650 4 $a Graphene. $3 1569149
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650 4 $a Lasers. $3 535503
650 4 $a Grain boundaries. $3 748639
650 4 $a Molybdenum. $3 3681682
650 4 $a Analytical chemistry. $3 3168300
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