東華大學圖書館 |

Language: English

Help

回圖書館首頁

手機版館藏查詢

Back

Switch To: Labeled | MARC Mode | ISBD

Source-Level Debugging for Hardware ...

Zhang, Keyi,

Linked to FindBook

Google Book

Amazon

博客來

Source-Level Debugging for Hardware Generator Frameworks /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Source-Level Debugging for Hardware Generator Frameworks // Keyi Zhang.
Author:	Zhang, Keyi,
Description:	1 electronic resource (151 pages)
Notes:	Source: Dissertations Abstracts International, Volume: 84-09, Section: B.
Contained By:	Dissertations Abstracts International84-09B.
Subject:	Programming languages. -
Online resource:	https://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=30306158
ISBN:	9798374476651

Source-Level Debugging for Hardware Generator Frameworks /
Zhang, Keyi,

Source-Level Debugging for Hardware Generator Frameworks /Keyi Zhang. - 1 electronic resource (151 pages)

Source: Dissertations Abstracts International, Volume: 84-09, Section: B.

Historically, hardware was specified manually in hardware description languages (HDLs) such as SystemVerilog and VHSIC Hardware Description Language (VHDL). Although these languages have evolved over the years, it is increasingly difficult for them to keep up with the trend of hardware customization and specialization, where a family of hardware is created with minor variants for different use cases. The parameterization and template language features offered in these HDLs can no longer satisfy the complex nature of hardware design, increasing the engineering cost [2]. In response to this problem, Ofer Shacham et al. [3] argued that we should rethink the traditional hardware design: instead of building a new customized chip for every application, we should reuse the design process to generate multiple new chips, which is done through a set of frameworks called hardware generators.Following the new design paradigm shift, designers have seen various hardware generator frameworks developed and used in practice over the past decade. Many frameworks are embedded into other high-level programming languages, i.e., embedded domain-specific languages (eDSL), such as magma [4] (Python) and Chisel [5] (Scala). This kind of framework requires designers to write a program in the eDSL, which later is executed or compiled to produce Register-Transfer Level (RTL). In these systems, the designers usually need to fully specify the cycle-level timing behavior of the hardware in the eDSL. This constraint is relaxed in High-Level Synthesis (HLS), another form of hardware generator, where designers specify only the high-level logic and scheduling directives: the compiler is responsible for producing a valid schedule given timing and resource constraints.Unfortunately, however, many features introduced in the frameworks to increase design productivity and synthesis quality make the generated RTL difficult for the designers to read and to understand. This is because the compiler transformations and optimizations often obfuscate the code. Since most intellectual property (IP) blocks are transferred at the RTL level, electronic design automation (EDA) engineers focus on optimizing RTL-level simulation and verification. As a result, any system-level verification has to be done at the RTL level, and hardware designers have to debug the system-level issues with RTL, which contains the generated code. Consequently, this generated code makes the generator frameworks difficult to debug [6, 7, 8].While it might be tempting to fix the debugging problem by removing hardware generators-after all, more time is spent on validation than design [9]-this would be a bad decision. In many eDSLfocused generator frameworks, the designer can use many host language features, such as objectoriented programming, functional programming, and complex data types, which offer stronger type safety guarantee. Because program execution involves many sequential stages, designers can instead use software languages to control the hardware generation process. These software programming techniques overcome the limitations of traditional HDLs and improve design productivity [5, 10, 6, 11].To continue to leverage these advantages, the work presented in this thesis demonstrates how we can apply source-level software debugging techniques to create a powerful debugging system for hardware generators. Software debugging systems are extremely useful for this purpose because they deal with problems in software similar to that discussed above, namely, when the execution environment, such as CPU or virtual machine instructions, is drastically different from the source code.

English

ISBN: 9798374476651Subjects--Topical Terms:

3683658
Programming languages.

Source-Level Debugging for Hardware Generator Frameworks /
LDR:05018nmm a22003853i 4500 001 2430617
005 20250527055717.5
006 m o d
007 cr|nu||||||||
008 261011s2022 miu||||||m |||||||eng d
020 $a 9798374476651
035 $a (MiAaPQD)AAI30306158
035 $a (MiAaPQD)STANFORDwb864cp0807
035 $a AAI30306158
040 $a MiAaPQD $b eng $c MiAaPQD $e rda
100 1 $a Zhang, Keyi, $e author. $3 3819026
245 1 0 $a Source-Level Debugging for Hardware Generator Frameworks / $c Keyi Zhang.
264 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2022
300 $a 1 electronic resource (151 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Dissertations Abstracts International, Volume: 84-09, Section: B.
500 $a Advisors: Horowitz, Mark; Barrett, Clark; Asgar, Zain Committee members: Bent, Stacey F.
502 $b Ph.D. $c Stanford University $d 2022.
520 $a Historically, hardware was specified manually in hardware description languages (HDLs) such as SystemVerilog and VHSIC Hardware Description Language (VHDL). Although these languages have evolved over the years, it is increasingly difficult for them to keep up with the trend of hardware customization and specialization, where a family of hardware is created with minor variants for different use cases. The parameterization and template language features offered in these HDLs can no longer satisfy the complex nature of hardware design, increasing the engineering cost [2]. In response to this problem, Ofer Shacham et al. [3] argued that we should rethink the traditional hardware design: instead of building a new customized chip for every application, we should reuse the design process to generate multiple new chips, which is done through a set of frameworks called hardware generators.Following the new design paradigm shift, designers have seen various hardware generator frameworks developed and used in practice over the past decade. Many frameworks are embedded into other high-level programming languages, i.e., embedded domain-specific languages (eDSL), such as magma [4] (Python) and Chisel [5] (Scala). This kind of framework requires designers to write a program in the eDSL, which later is executed or compiled to produce Register-Transfer Level (RTL). In these systems, the designers usually need to fully specify the cycle-level timing behavior of the hardware in the eDSL. This constraint is relaxed in High-Level Synthesis (HLS), another form of hardware generator, where designers specify only the high-level logic and scheduling directives: the compiler is responsible for producing a valid schedule given timing and resource constraints.Unfortunately, however, many features introduced in the frameworks to increase design productivity and synthesis quality make the generated RTL difficult for the designers to read and to understand. This is because the compiler transformations and optimizations often obfuscate the code. Since most intellectual property (IP) blocks are transferred at the RTL level, electronic design automation (EDA) engineers focus on optimizing RTL-level simulation and verification. As a result, any system-level verification has to be done at the RTL level, and hardware designers have to debug the system-level issues with RTL, which contains the generated code. Consequently, this generated code makes the generator frameworks difficult to debug [6, 7, 8].While it might be tempting to fix the debugging problem by removing hardware generators-after all, more time is spent on validation than design [9]-this would be a bad decision. In many eDSLfocused generator frameworks, the designer can use many host language features, such as objectoriented programming, functional programming, and complex data types, which offer stronger type safety guarantee. Because program execution involves many sequential stages, designers can instead use software languages to control the hardware generation process. These software programming techniques overcome the limitations of traditional HDLs and improve design productivity [5, 10, 6, 11].To continue to leverage these advantages, the work presented in this thesis demonstrates how we can apply source-level software debugging techniques to create a powerful debugging system for hardware generators. Software debugging systems are extremely useful for this purpose because they deal with problems in software similar to that discussed above, namely, when the execution environment, such as CPU or virtual machine instructions, is drastically different from the source code.
546 $a English
590 $a School code: 0212
650 4 $a Programming languages. $3 3683658
650 4 $a Debugging. $3 3689317
650 4 $a Software upgrading. $3 3680542
650 4 $a Computer science. $3 523869
690 $a 0984
710 2 $a Stanford University. $e degree granting institution. $3 3765820
720 1 $a Horowitz, Mark $e degree supervisor.
720 1 $a Barrett, Clark $e degree supervisor.
720 1 $a Asgar, Zain $e degree supervisor.
773 0 $t Dissertations Abstracts International $g 84-09B.
790 $a 0212
791 $a Ph.D.
792 $a 2022
856 4 0 $u https://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=30306158