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Developing Fpgas as an Acceleration ...

Thomas, James Joe.

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Developing Fpgas as an Acceleration Platform for Data-Intensive Applications.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Developing Fpgas as an Acceleration Platform for Data-Intensive Applications./
作者:	Thomas, James Joe.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2022,
面頁冊數:	72 p.
附註:	Source: Dissertations Abstracts International, Volume: 84-04, Section: B.
Contained By:	Dissertations Abstracts International84-04B.
標題:	Language. -
電子資源:	https://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=29342246
ISBN:	9798352602911

Developing Fpgas as an Acceleration Platform for Data-Intensive Applications.
Thomas, James Joe.

Developing Fpgas as an Acceleration Platform for Data-Intensive Applications. - Ann Arbor : ProQuest Dissertations & Theses, 2022 - 72 p.

Source: Dissertations Abstracts International, Volume: 84-04, Section: B.

Thesis (Ph.D.)--Stanford University, 2022.

FPGAs have grown in popularity as compute accelerators in recent years, being deployed in the clouds of Amazon, Alibaba, and Microsoft for either internal tasks like networking acceleration or directly for customers to rent. As their use has grown, it has become increasingly clear that they are fairly unproductive for developers compared to competing platforms like GPUs and CPUs. We aim to close this gap in this dissertation by taking a domain-specific approach. We argue that general-purpose FPGA development tools are fundamentally limited by the complexity of the platform, and therefore focus on building faster and simpler tools for the specific case of streaming data-intensive applications.We first present Fleet, a system for accelerating massively parallel streaming workloads on FPGAs. Fleet provides a simple language for users to define a compute unit that processes a single stream of data, and then automatically replicates the compute unit many times into a memory controller fabric so that the final design can process many independent streams at once. We next present a fast compilation system for Fleet-like applications. Our system leverages the fact that the memory controller design is fixed across applications, and therefore compiles it ahead of time, leaving empty slots for copies of the user's processing unit. The user-visible compile time is thus reduced only to the time required to compile a few copies of the processing unit and replicate them into the prebuilt memory controller. Finally, we leverage the design patterns of identical compute units and streaming DRAM access to design a FPGA accelerator for the problem of finding interesting subgroups in large tabular datasets. This accelerator is able to outperform GPUs and CPUs on a cost per throughput basis due to its customized partitioning of SRAM resources across compute units.

ISBN: 9798352602911Subjects--Topical Terms:

643551
Language.

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