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Enabling Reliable Processing-in-Memo...

Ollivier, Sebastien Sylvain JeanLuc.

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Enabling Reliable Processing-in-Memory Augmented Storage for Spintronic Domain Wall Memory through Transverse Read.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Enabling Reliable Processing-in-Memory Augmented Storage for Spintronic Domain Wall Memory through Transverse Read./
Author:	Ollivier, Sebastien Sylvain JeanLuc.
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2022,
Description:	149 p.
Notes:	Source: Dissertations Abstracts International, Volume: 84-04, Section: B.
Contained By:	Dissertations Abstracts International84-04B.
Subject:	Nanowires. -
Online resource:	https://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=29335748
ISBN:	9798352602744

Enabling Reliable Processing-in-Memory Augmented Storage for Spintronic Domain Wall Memory through Transverse Read.
Ollivier, Sebastien Sylvain JeanLuc.

Enabling Reliable Processing-in-Memory Augmented Storage for Spintronic Domain Wall Memory through Transverse Read. - Ann Arbor : ProQuest Dissertations & Theses, 2022 - 149 p.

Source: Dissertations Abstracts International, Volume: 84-04, Section: B.

Thesis (Ph.D.)--University of Pittsburgh, 2022.

In recent years, more and more proposals have been explored to replace conventional SRAM, DRAM, and Flash with novel memories. Moreover, the performance gap between data access latency over a memory bus and high-speed processing continues to grow. Domain Wall Memory (DWM)-aka Racetrack Memory-is a spintronic memory that stores multiple data bits in a ferromagnetic nanowire and shifts this data into alignment with one or few access ports to read/write the data. DWM is non-volatile, highly dense (1-4F2 per cell), extremely energy efficient (circa 0.1pJ per write), low latency (circa 1ns per access), and does not suffer from endurance limitations. Domain Wall Memory can serve as an ideal conventional memory/storage replacement throughout the memory hierarchy from cache replacement to main memory.DWM's main drawback is the latency, energy, and potential reliability concern from shifting data to align with access points. However, this structure also permits a novel recently proposed access mode called a Transverse Read (TR), which determines the number of '1's between two access points without pin-pointing their location. This dissertation leverages TR to first propose two new reliability schemes that address misalignment and data loss in DWM due to pinning while shifting. Second, a TR-based Processing-In-Memory (PIM) architecture is proposed that boasts multi-operand bulk-bitwise operations, logical shifting and rotation, multi-operand addition, two operand multiplication, and dense accumulators. The arithmetic operations are shown for Integer/fixed-point and floating-point fidelities. Third, targeting DWM in size, weight, and power (SWaP) constrained architectures such as edge systems multiple applications of DWM PIM are explored including machine learning inference and training for hyperdimensional computing, convolutional neural networks.The proposed reliability improvements offer 10's of years of fault free operation with energy savings and protection over new fault modes compared to prior work. The proposed PIM provides multiple factors over improvements in performance and energy compared to prior PIM work dedicated accelerators and often dedicated application specific integrated circuits (ASICs).

ISBN: 9798352602744Subjects--Topical Terms:

576100
Nanowires.

Enabling Reliable Processing-in-Memory Augmented Storage for Spintronic Domain Wall Memory through Transverse Read.
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520 $a In recent years, more and more proposals have been explored to replace conventional SRAM, DRAM, and Flash with novel memories. Moreover, the performance gap between data access latency over a memory bus and high-speed processing continues to grow. Domain Wall Memory (DWM)-aka Racetrack Memory-is a spintronic memory that stores multiple data bits in a ferromagnetic nanowire and shifts this data into alignment with one or few access ports to read/write the data. DWM is non-volatile, highly dense (1-4F2 per cell), extremely energy efficient (circa 0.1pJ per write), low latency (circa 1ns per access), and does not suffer from endurance limitations. Domain Wall Memory can serve as an ideal conventional memory/storage replacement throughout the memory hierarchy from cache replacement to main memory.DWM's main drawback is the latency, energy, and potential reliability concern from shifting data to align with access points. However, this structure also permits a novel recently proposed access mode called a Transverse Read (TR), which determines the number of '1's between two access points without pin-pointing their location. This dissertation leverages TR to first propose two new reliability schemes that address misalignment and data loss in DWM due to pinning while shifting. Second, a TR-based Processing-In-Memory (PIM) architecture is proposed that boasts multi-operand bulk-bitwise operations, logical shifting and rotation, multi-operand addition, two operand multiplication, and dense accumulators. The arithmetic operations are shown for Integer/fixed-point and floating-point fidelities. Third, targeting DWM in size, weight, and power (SWaP) constrained architectures such as edge systems multiple applications of DWM PIM are explored including machine learning inference and training for hyperdimensional computing, convolutional neural networks.The proposed reliability improvements offer 10's of years of fault free operation with energy savings and protection over new fault modes compared to prior work. The proposed PIM provides multiple factors over improvements in performance and energy compared to prior PIM work dedicated accelerators and often dedicated application specific integrated circuits (ASICs).
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