Language:
English
繁體中文
Help
回圖書館首頁
手機版館藏查詢
Login
Back
Switch To:
Labeled
|
MARC Mode
|
ISBD
High energy efficiency neural networ...
~
Yue, Jinshan.
Linked to FindBook
Google Book
Amazon
博客來
High energy efficiency neural network processor with combined digital and computing-in-memory architecture
Record Type:
Electronic resources : Monograph/item
Title/Author:
High energy efficiency neural network processor with combined digital and computing-in-memory architecture/ by Jinshan Yue.
Author:
Yue, Jinshan.
Published:
Singapore :Springer Nature Singapore : : 2024.,
Description:
xvi, 118 p. :ill. (chiefly col.), digital ;24 cm.
Notes:
"Doctoral thesis accepted by Tsinghua University, Beijing, China."
[NT 15003449]:
Introduction -- Basis and research status of neural network processor -- Neural network processor for specific kernel optimized data reuse -- Neural network processor with frequency domain compression algorithm optimization -- Neural network processor combining digital and computing in memory architecture -- Digital computing in memory neural network processor supporting large scale models -- Conclusion and prospect.
Contained By:
Springer Nature eBook
Subject:
Neural networks (Computer science) -
Online resource:
https://doi.org/10.1007/978-981-97-3477-1
ISBN:
9789819734771
High energy efficiency neural network processor with combined digital and computing-in-memory architecture
Yue, Jinshan.
High energy efficiency neural network processor with combined digital and computing-in-memory architecture
[electronic resource] /by Jinshan Yue. - Singapore :Springer Nature Singapore :2024. - xvi, 118 p. :ill. (chiefly col.), digital ;24 cm. - Springer theses,2190-5061. - Springer theses..
"Doctoral thesis accepted by Tsinghua University, Beijing, China."
Introduction -- Basis and research status of neural network processor -- Neural network processor for specific kernel optimized data reuse -- Neural network processor with frequency domain compression algorithm optimization -- Neural network processor combining digital and computing in memory architecture -- Digital computing in memory neural network processor supporting large scale models -- Conclusion and prospect.
Neural network (NN) algorithms are driving the rapid development of modern artificial intelligence (AI) The energy-efficient NN processor has become an urgent requirement for the practical NN applications on widespread low-power AI devices. To address this challenge, this dissertation investigates pure-digital and digital computing-in-memory (digital-CIM) solutions and carries out four major studies. For pure-digital NN processors, this book analyses the insufficient data reuse in conventional architectures and proposes a kernel-optimized NN processor. This dissertation adopts a structural frequency-domain compression algorithm, named CirCNN. The fabricated processor shows 8.1x/4.2x area/energy efficiency compared to the state-of-the-art NN processor. For digital-CIM NN processors, this dissertation combines the flexibility of digital circuits with the high energy efficiency of CIM. The fabricated CIM processor validates the sparsity improvement of the CIM architecture for the first time. This dissertation further designs a processor that considers the weight updating problem on the CIM architecture for the first time. This dissertation demonstrates that the combination of digital and CIM circuits is a promising technical route for an energy-efficient NN processor, which can promote the large-scale application of low-power AI devices.
ISBN: 9789819734771
Standard No.: 10.1007/978-981-97-3477-1doiSubjects--Topical Terms:
532070
Neural networks (Computer science)
LC Class. No.: QA76.87
Dewey Class. No.: 006.32
High energy efficiency neural network processor with combined digital and computing-in-memory architecture
LDR
:02928nmm a2200349 a 4500
001
2374250
003
DE-He213
005
20240802130230.0
006
m d
007
cr nn 008maaau
008
241231s2024 si s 0 eng d
020
$a
9789819734771
$q
(electronic bk.)
020
$a
9789819734764
$q
(paper)
024
7
$a
10.1007/978-981-97-3477-1
$2
doi
035
$a
978-981-97-3477-1
040
$a
GP
$c
GP
041
0
$a
eng
050
4
$a
QA76.87
072
7
$a
TJF
$2
bicssc
072
7
$a
TEC008000
$2
bisacsh
072
7
$a
TJF
$2
thema
082
0 4
$a
006.32
$2
23
090
$a
QA76.87
$b
.Y94 2024
100
1
$a
Yue, Jinshan.
$3
3722964
245
1 0
$a
High energy efficiency neural network processor with combined digital and computing-in-memory architecture
$h
[electronic resource] /
$c
by Jinshan Yue.
260
$a
Singapore :
$b
Springer Nature Singapore :
$b
Imprint: Springer,
$c
2024.
300
$a
xvi, 118 p. :
$b
ill. (chiefly col.), digital ;
$c
24 cm.
490
1
$a
Springer theses,
$x
2190-5061
500
$a
"Doctoral thesis accepted by Tsinghua University, Beijing, China."
505
0
$a
Introduction -- Basis and research status of neural network processor -- Neural network processor for specific kernel optimized data reuse -- Neural network processor with frequency domain compression algorithm optimization -- Neural network processor combining digital and computing in memory architecture -- Digital computing in memory neural network processor supporting large scale models -- Conclusion and prospect.
520
$a
Neural network (NN) algorithms are driving the rapid development of modern artificial intelligence (AI) The energy-efficient NN processor has become an urgent requirement for the practical NN applications on widespread low-power AI devices. To address this challenge, this dissertation investigates pure-digital and digital computing-in-memory (digital-CIM) solutions and carries out four major studies. For pure-digital NN processors, this book analyses the insufficient data reuse in conventional architectures and proposes a kernel-optimized NN processor. This dissertation adopts a structural frequency-domain compression algorithm, named CirCNN. The fabricated processor shows 8.1x/4.2x area/energy efficiency compared to the state-of-the-art NN processor. For digital-CIM NN processors, this dissertation combines the flexibility of digital circuits with the high energy efficiency of CIM. The fabricated CIM processor validates the sparsity improvement of the CIM architecture for the first time. This dissertation further designs a processor that considers the weight updating problem on the CIM architecture for the first time. This dissertation demonstrates that the combination of digital and CIM circuits is a promising technical route for an energy-efficient NN processor, which can promote the large-scale application of low-power AI devices.
650
0
$a
Neural networks (Computer science)
$3
532070
650
1 4
$a
Electronics and Microelectronics, Instrumentation.
$3
893838
650
2 4
$a
Electronic Circuits and Systems.
$3
3538814
650
2 4
$a
Processor Architectures.
$3
892680
650
2 4
$a
Computational Intelligence.
$3
1001631
710
2
$a
SpringerLink (Online service)
$3
836513
773
0
$t
Springer Nature eBook
830
0
$a
Springer theses.
$3
1314442
856
4 0
$u
https://doi.org/10.1007/978-981-97-3477-1
950
$a
Engineering (SpringerNature-11647)
based on 0 review(s)
Location:
ALL
電子資源
Year:
Volume Number:
Items
1 records • Pages 1 •
1
Inventory Number
Location Name
Item Class
Material type
Call number
Usage Class
Loan Status
No. of reservations
Opac note
Attachments
W9494699
電子資源
11.線上閱覽_V
電子書
EB QA76.87
一般使用(Normal)
On shelf
0
1 records • Pages 1 •
1
Multimedia
Reviews
Add a review
and share your thoughts with other readers
Export
pickup library
Processing
...
Change password
Login