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Understanding logic locking

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Understanding logic locking/ by Kimia Zamiri Azar ... [et al.].
其他作者:	Azar, Kimia Zamiri.
出版者:	Cham :Springer International Publishing : : 2024.,
面頁冊數:	xvi, 381 p. :ill., digital ;24 cm.
內容註:	Basics of VLSI Design -- Basics of VLSI Testing and Debug -- IP Protection in VLSI Design: A Historical View -- Making a Case for Logic Locking -- Fundamentals of Logic Locking -- Infrastructure around Logic Locking -- Impact of Satisfiability Solvers on Logic Locking -- Post-Satisfiability Era: Countermeasures and Threats -- Design-for-Testability and its Impact on Logic Locking -- Emergence of Cutting-edge Technologies on Logic Locking -- Logic Locking in Future IC Supply Chain Environments -- Multilayer Approach to Logic Locking -- A Step-by-Step Guide for Protecting/Locking Your IP -- A Step-by-Step Guide for Security Evaluation of Protected/Locked IP.
Contained By:	Springer Nature eBook
標題:	Computer security. -
電子資源:	https://doi.org/10.1007/978-3-031-37989-5
ISBN:	9783031379895

Understanding logic locking
Understanding logic locking[electronic resource] /by Kimia Zamiri Azar ... [et al.]. - Cham :Springer International Publishing :2024. - xvi, 381 p. :ill., digital ;24 cm.

Basics of VLSI Design -- Basics of VLSI Testing and Debug -- IP Protection in VLSI Design: A Historical View -- Making a Case for Logic Locking -- Fundamentals of Logic Locking -- Infrastructure around Logic Locking -- Impact of Satisfiability Solvers on Logic Locking -- Post-Satisfiability Era: Countermeasures and Threats -- Design-for-Testability and its Impact on Logic Locking -- Emergence of Cutting-edge Technologies on Logic Locking -- Logic Locking in Future IC Supply Chain Environments -- Multilayer Approach to Logic Locking -- A Step-by-Step Guide for Protecting/Locking Your IP -- A Step-by-Step Guide for Security Evaluation of Protected/Locked IP.

This book demonstrates the breadth and depth of IP protection through logic locking, considering both attacker/adversary and defender/designer perspectives. The authors draw a semi-chronological picture of the evolution of logic locking during the last decade, gathering and describing all the DO's and DON'Ts in this approach. They describe simple-to-follow scenarios and guide readers to navigate/identify threat models and design/evaluation flow for further studies. Readers will gain a comprehensive understanding of all fundamentals of logic locking. Covers modern VLSI design, testability and debug, and hardware security threats at different levels of abstraction; Provides a comprehensive overview of logic locking techniques and their applications to hardware security; Covers logic locking from implementation to evaluation, different assumptions, models and abstraction layers.

ISBN: 9783031379895

Standard No.: 10.1007/978-3-031-37989-5doiSubjects--Topical Terms:

540555
Computer security.

LC Class. No.: QA76.9.A25

Dewey Class. No.: 005.8

Understanding logic locking
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505 0 $a Basics of VLSI Design -- Basics of VLSI Testing and Debug -- IP Protection in VLSI Design: A Historical View -- Making a Case for Logic Locking -- Fundamentals of Logic Locking -- Infrastructure around Logic Locking -- Impact of Satisfiability Solvers on Logic Locking -- Post-Satisfiability Era: Countermeasures and Threats -- Design-for-Testability and its Impact on Logic Locking -- Emergence of Cutting-edge Technologies on Logic Locking -- Logic Locking in Future IC Supply Chain Environments -- Multilayer Approach to Logic Locking -- A Step-by-Step Guide for Protecting/Locking Your IP -- A Step-by-Step Guide for Security Evaluation of Protected/Locked IP.
520 $a This book demonstrates the breadth and depth of IP protection through logic locking, considering both attacker/adversary and defender/designer perspectives. The authors draw a semi-chronological picture of the evolution of logic locking during the last decade, gathering and describing all the DO's and DON'Ts in this approach. They describe simple-to-follow scenarios and guide readers to navigate/identify threat models and design/evaluation flow for further studies. Readers will gain a comprehensive understanding of all fundamentals of logic locking. Covers modern VLSI design, testability and debug, and hardware security threats at different levels of abstraction; Provides a comprehensive overview of logic locking techniques and their applications to hardware security; Covers logic locking from implementation to evaluation, different assumptions, models and abstraction layers.
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650 2 4 $a Electronic Circuits and Systems. $3 3538814
700 1 $a Azar, Kimia Zamiri. $3 3711320
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