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Towards heterogeneous multi-core systems-on-chip for edge machine learning = journey from single-core acceleration to multi-core heterogeneous systems /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Towards heterogeneous multi-core systems-on-chip for edge machine learning/ by Vikram Jain, Marian Verhelst.
Reminder of title:	journey from single-core acceleration to multi-core heterogeneous systems /
Author:	Jain, Vikram.
other author:	Verhelst, Marian.
Published:	Cham :Springer Nature Switzerland : : 2024.,
Description:	xxiii, 186 p. :ill. (some col.), digital ;24 cm.
[NT 15003449]:	Chapter 1: Introduction -- Chapter 2 Algorithmic Background for Machine Learning -- Chapter 3 Scoping the Landscape of (Extreme) Edge Machine Learning Processors -- Chapter 4 Hardware-Software Co-optimization through Design Space Exploration -- Chapter 5 Energy Efficient Single-core Hardware Acceleration -- Chapter 6 TinyVers: A Tiny Versatile All-Digital Heterogeneous Multi-core System-on-Chip -- Chapter 7 DIANA: Digital and ANAlog Heterogeneous Multi-core System-on-Chip -- Chapter 8 Networks-on-chip to Enable Large-scale Multi-core ML Acceleration -- Chapter 9 Conclusion.
Contained By:	Springer Nature eBook
Subject:	Systems on a chip - Design and construction. -
Online resource:	https://doi.org/10.1007/978-3-031-38230-7
ISBN:	9783031382307

Towards heterogeneous multi-core systems-on-chip for edge machine learning = journey from single-core acceleration to multi-core heterogeneous systems /
Jain, Vikram.

Towards heterogeneous multi-core systems-on-chip for edge machine learningjourney from single-core acceleration to multi-core heterogeneous systems /[electronic resource] :by Vikram Jain, Marian Verhelst. - Cham :Springer Nature Switzerland :2024. - xxiii, 186 p. :ill. (some col.), digital ;24 cm.

Chapter 1: Introduction -- Chapter 2 Algorithmic Background for Machine Learning -- Chapter 3 Scoping the Landscape of (Extreme) Edge Machine Learning Processors -- Chapter 4 Hardware-Software Co-optimization through Design Space Exploration -- Chapter 5 Energy Efficient Single-core Hardware Acceleration -- Chapter 6 TinyVers: A Tiny Versatile All-Digital Heterogeneous Multi-core System-on-Chip -- Chapter 7 DIANA: Digital and ANAlog Heterogeneous Multi-core System-on-Chip -- Chapter 8 Networks-on-chip to Enable Large-scale Multi-core ML Acceleration -- Chapter 9 Conclusion.

This book explores and motivates the need for building homogeneous and heterogeneous multi-core systems for machine learning to enable flexibility and energy-efficiency. Coverage focuses on a key aspect of the challenges of (extreme-)edge-computing, i.e., design of energy-efficient and flexible hardware architectures, and hardware-software co-optimization strategies to enable early design space exploration of hardware architectures. The authors investigate possible design solutions for building single-core specialized hardware accelerators for machine learning and motivates the need for building homogeneous and heterogeneous multi-core systems to enable flexibility and energy-efficiency. The advantages of scaling to heterogeneous multi-core systems are shown through the implementation of multiple test chips and architectural optimizations. Discusses the need for scaling to multi-core systems for machine learning and several architectural and software optimizations; Covers single-core, homogeneous and heterogeneous multi-core Systems-on-chip for machine learning applications; Discusses the benefits of heterogeneity in the context of machine learning.

ISBN: 9783031382307

Standard No.: 10.1007/978-3-031-38230-7doiSubjects--Topical Terms:

745351
Systems on a chip
--Design and construction.

LC Class. No.: TK7895.E42 / J35 2024

Dewey Class. No.: 621.3815

Towards heterogeneous multi-core systems-on-chip for edge machine learning = journey from single-core acceleration to multi-core heterogeneous systems /
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505 0 $a Chapter 1: Introduction -- Chapter 2 Algorithmic Background for Machine Learning -- Chapter 3 Scoping the Landscape of (Extreme) Edge Machine Learning Processors -- Chapter 4 Hardware-Software Co-optimization through Design Space Exploration -- Chapter 5 Energy Efficient Single-core Hardware Acceleration -- Chapter 6 TinyVers: A Tiny Versatile All-Digital Heterogeneous Multi-core System-on-Chip -- Chapter 7 DIANA: Digital and ANAlog Heterogeneous Multi-core System-on-Chip -- Chapter 8 Networks-on-chip to Enable Large-scale Multi-core ML Acceleration -- Chapter 9 Conclusion.
520 $a This book explores and motivates the need for building homogeneous and heterogeneous multi-core systems for machine learning to enable flexibility and energy-efficiency. Coverage focuses on a key aspect of the challenges of (extreme-)edge-computing, i.e., design of energy-efficient and flexible hardware architectures, and hardware-software co-optimization strategies to enable early design space exploration of hardware architectures. The authors investigate possible design solutions for building single-core specialized hardware accelerators for machine learning and motivates the need for building homogeneous and heterogeneous multi-core systems to enable flexibility and energy-efficiency. The advantages of scaling to heterogeneous multi-core systems are shown through the implementation of multiple test chips and architectural optimizations. Discusses the need for scaling to multi-core systems for machine learning and several architectural and software optimizations; Covers single-core, homogeneous and heterogeneous multi-core Systems-on-chip for machine learning applications; Discusses the benefits of heterogeneity in the context of machine learning.
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