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Synthesizable Mixed-Signal Building Blocks for Open Source High Speed Serial Links.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Synthesizable Mixed-Signal Building Blocks for Open Source High Speed Serial Links./
Author:	Kim, Sung-Jin .
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2021,
Description:	160 p.
Notes:	Source: Dissertations Abstracts International, Volume: 83-05, Section: B.
Contained By:	Dissertations Abstracts International83-05B.
Subject:	Internet. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=28688378
ISBN:	9798544204237

Synthesizable Mixed-Signal Building Blocks for Open Source High Speed Serial Links.
Kim, Sung-Jin .

Synthesizable Mixed-Signal Building Blocks for Open Source High Speed Serial Links. - Ann Arbor : ProQuest Dissertations & Theses, 2021 - 160 p.

Source: Dissertations Abstracts International, Volume: 83-05, Section: B.

Thesis (Ph.D.)--Stanford University, 2021.

This item must not be sold to any third party vendors.

The advent of the Internet, coupled with advances in IC fabrication technology, has dramatically changed our lives. We are always connected to the cloud to easily access, and share information and a variety of electronic devices make us more productive. The amount of data transferred through the Internet continues to grow exponentially as shown in Figure 1.1(a) [1]. In 2017, 120 exabytes of data was transferred per month, whereas today, only 4 years later, the traffic has grown to 320 exabytes, about 3 times more than 2017. The ever-growing Internet traffic requires appropriate network communication to support it, which is manifested by the data rate road map of the Ethernet standard shown in Figure 1.1(b) [2].On the other hand, as integration density and processing bandwidth keep increasing, a system on a chip (SoC) can support fancier applications, such as machine learning, AI, and high performance computing. However, these new applications create demand for higher I/O throughput to connect the chip to memories and peripherals. Figure 1.1(c) [3] is the data rate road map of PCIe, which is one of the most popular standards for high-speed peripherals, showing a thirst for higher I/O throughput. Figure 1.1(d) [4] clearly shows the importance and demand for high-speed wireline data links, which constitute about a quarter of today's entire silicon IP market.These standard communication protocols are defined by the open systems interconnection (OSI) model [5], which consists of seven abstraction layers. The physical layer, or PHY, is the layer that directly interacts with a physical media (channel) and is responsible for the transmission and reception of unstructured raw data between a device and the medium. For the rest of this dissertation, the term "link" refers to the PHY layer of a wireline communication link.Compared to today's complex functions on an SoC, the function of the I/O seems extremely simple: its only purpose is sending ones and zeros through a wire and successfully receiving them. However, when we want to make the throughput of the I/O tens of gigabits per second (Gbps), this task is no longer simple. The transmitted signal experiences frequency-dependent energy loss due to the inherent band-limited characteristic of the physical channel, resulting in severe distortion of the received waveform. Significant effort goes into developing better communication channels, ranging from more advanced printed circuit boards (PCBs), chip packages, and connectors. Meanwhile, most high-speed serial links today employ multiple signal processing techniques to overcome the bandwidth limitations of legacy channels.Until about a decade ago, the architecture of high-speed serial links had converged into a "golden architecture," also known as the mixed-signal architecture, shown in Figure 1.2(a) [6][7][8]. Continuous-time linear equalizers (CTLEs), variable gain amplifiers (VGAs), feed-forward equalizers (FFEs), and decision-feedback equalizers (DFEs) are commonly employed to compensate for the effect of channel loss. Dualloop clock and data recovery (CDR) with an oversampling phase detector (PD) is the most popular approach to achieve symbol synchronization, and a phase-locked loop (PLL)-based clock generator with a phase interpolator (PI) usually provides the optimal sampling clocks for the PD.

ISBN: 9798544204237Subjects--Topical Terms:

527226
Internet.

Synthesizable Mixed-Signal Building Blocks for Open Source High Speed Serial Links.
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506 $a This item must not be sold to any third party vendors.
520 $a The advent of the Internet, coupled with advances in IC fabrication technology, has dramatically changed our lives. We are always connected to the cloud to easily access, and share information and a variety of electronic devices make us more productive. The amount of data transferred through the Internet continues to grow exponentially as shown in Figure 1.1(a) [1]. In 2017, 120 exabytes of data was transferred per month, whereas today, only 4 years later, the traffic has grown to 320 exabytes, about 3 times more than 2017. The ever-growing Internet traffic requires appropriate network communication to support it, which is manifested by the data rate road map of the Ethernet standard shown in Figure 1.1(b) [2].On the other hand, as integration density and processing bandwidth keep increasing, a system on a chip (SoC) can support fancier applications, such as machine learning, AI, and high performance computing. However, these new applications create demand for higher I/O throughput to connect the chip to memories and peripherals. Figure 1.1(c) [3] is the data rate road map of PCIe, which is one of the most popular standards for high-speed peripherals, showing a thirst for higher I/O throughput. Figure 1.1(d) [4] clearly shows the importance and demand for high-speed wireline data links, which constitute about a quarter of today's entire silicon IP market.These standard communication protocols are defined by the open systems interconnection (OSI) model [5], which consists of seven abstraction layers. The physical layer, or PHY, is the layer that directly interacts with a physical media (channel) and is responsible for the transmission and reception of unstructured raw data between a device and the medium. For the rest of this dissertation, the term "link" refers to the PHY layer of a wireline communication link.Compared to today's complex functions on an SoC, the function of the I/O seems extremely simple: its only purpose is sending ones and zeros through a wire and successfully receiving them. However, when we want to make the throughput of the I/O tens of gigabits per second (Gbps), this task is no longer simple. The transmitted signal experiences frequency-dependent energy loss due to the inherent band-limited characteristic of the physical channel, resulting in severe distortion of the received waveform. Significant effort goes into developing better communication channels, ranging from more advanced printed circuit boards (PCBs), chip packages, and connectors. Meanwhile, most high-speed serial links today employ multiple signal processing techniques to overcome the bandwidth limitations of legacy channels.Until about a decade ago, the architecture of high-speed serial links had converged into a "golden architecture," also known as the mixed-signal architecture, shown in Figure 1.2(a) [6][7][8]. Continuous-time linear equalizers (CTLEs), variable gain amplifiers (VGAs), feed-forward equalizers (FFEs), and decision-feedback equalizers (DFEs) are commonly employed to compensate for the effect of channel loss. Dualloop clock and data recovery (CDR) with an oversampling phase detector (PD) is the most popular approach to achieve symbol synchronization, and a phase-locked loop (PLL)-based clock generator with a phase interpolator (PI) usually provides the optimal sampling clocks for the PD.
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