東華大學圖書館 |

Language: English

Help

回圖書館首頁

手機版館藏查詢

Back

Switch To: Labeled | MARC Mode | ISBD

Adaptive digital circuits for power-...

Jain, Saurabh.

Linked to FindBook

Google Book

Amazon

博客來

Adaptive digital circuits for power-performance range beyond wide voltage scaling = from the clock path to the data path /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Adaptive digital circuits for power-performance range beyond wide voltage scaling/ by Saurabh Jain, Longyang Lin, Massimo Alioto.
Reminder of title:	from the clock path to the data path /
Author:	Jain, Saurabh.
other author:	Lin, Longyang.
Published:	Cham :Springer International Publishing : : 2020.,
Description:	xvi, 166 p. :ill., digital ;24 cm.
[NT 15003449]:	Introduction to wide voltage scaling, applications and challenges -- Reconfigurable microarchitectures down to pipestage and memory bank level -- Automated design flows and run-time optimization for reconfigurable microarchitectures -- Case studies of reconfigurable microarchitectures: accelerators, microprocessors and memories -- Reconfigurable clock networks, automated design flows, run-time optimization and case study -- Conclusion.
Contained By:	Springer eBooks
Subject:	Digital electronics. -
Online resource:	https://doi.org/10.1007/978-3-030-38796-9
ISBN:	9783030387969

Adaptive digital circuits for power-performance range beyond wide voltage scaling = from the clock path to the data path /
Jain, Saurabh.

Adaptive digital circuits for power-performance range beyond wide voltage scalingfrom the clock path to the data path /[electronic resource] :by Saurabh Jain, Longyang Lin, Massimo Alioto. - Cham :Springer International Publishing :2020. - xvi, 166 p. :ill., digital ;24 cm.

Introduction to wide voltage scaling, applications and challenges -- Reconfigurable microarchitectures down to pipestage and memory bank level -- Automated design flows and run-time optimization for reconfigurable microarchitectures -- Case studies of reconfigurable microarchitectures: accelerators, microprocessors and memories -- Reconfigurable clock networks, automated design flows, run-time optimization and case study -- Conclusion.

This book offers the first comprehensive coverage of digital design techniques to expand the power-performance tradeoff well beyond that allowed by conventional wide voltage scaling. Compared to conventional fixed designs, the approach described in this book makes digital circuits more versatile and adaptive, allowing simultaneous optimization at both ends of the power-performance spectrum. Drop-in solutions for fully automated and low-effort design based on commercial CAD tools are discussed extensively for processors, accelerators and on-chip memories, and are applicable to prominent applications (e.g., IoT, AI, wearables, biomedical) Through the higher power-performance versatility techniques described in this book, readers are enabled to reduce the design effort through reuse of the same digital design instance, across a wide range of applications. All concepts the authors discuss are demonstrated by dedicated testchip designs and experimental results. To make the results immediately usable by the reader, all the scripts necessary to create automated design flows based on commercial tools are provided and explained. Provides extensive coverage of the challenges and the key technologies enabling wide power-performance range in digital sub-systems (e.g., processors, memories, accelerators); Includes in-depth description of silicon-proven methodologies to design reconfigurable data path and clock path; Describes techniques for reconfigurable microarchitectures, down to the pipestage and the clock repeater level; Uses a highly interdisciplinary approach covering the circuit, the microarchitectural and the system levels of abstraction; Presents practical design examples and the related methodologies; Offers complementary design files and scripts, useful to replicate the presented developments and develop new designs.

ISBN: 9783030387969

Standard No.: 10.1007/978-3-030-38796-9doiSubjects--Topical Terms:

584066
Digital electronics.

LC Class. No.: TK7868.D5 / J356 2020

Dewey Class. No.: 621.3815

Adaptive digital circuits for power-performance range beyond wide voltage scaling = from the clock path to the data path /
LDR:03343nmm a2200325 a 4500 001 2216321
003 DE-He213
005 20200714115231.0
006 m d
007 cr nn 008maaau
008 201120s2020 sz s 0 eng d
020 $a 9783030387969 $q (electronic bk.)
020 $a 9783030387952 $q (paper)
024 7 $a 10.1007/978-3-030-38796-9 $2 doi
035 $a 978-3-030-38796-9
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7868.D5 $b J356 2020
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
090 $a TK7868.D5 $b J25 2020
100 1 $a Jain, Saurabh. $3 3413403
245 1 0 $a Adaptive digital circuits for power-performance range beyond wide voltage scaling $h [electronic resource] : $b from the clock path to the data path / $c by Saurabh Jain, Longyang Lin, Massimo Alioto.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2020.
300 $a xvi, 166 p. : $b ill., digital ; $c 24 cm.
505 0 $a Introduction to wide voltage scaling, applications and challenges -- Reconfigurable microarchitectures down to pipestage and memory bank level -- Automated design flows and run-time optimization for reconfigurable microarchitectures -- Case studies of reconfigurable microarchitectures: accelerators, microprocessors and memories -- Reconfigurable clock networks, automated design flows, run-time optimization and case study -- Conclusion.
520 $a This book offers the first comprehensive coverage of digital design techniques to expand the power-performance tradeoff well beyond that allowed by conventional wide voltage scaling. Compared to conventional fixed designs, the approach described in this book makes digital circuits more versatile and adaptive, allowing simultaneous optimization at both ends of the power-performance spectrum. Drop-in solutions for fully automated and low-effort design based on commercial CAD tools are discussed extensively for processors, accelerators and on-chip memories, and are applicable to prominent applications (e.g., IoT, AI, wearables, biomedical) Through the higher power-performance versatility techniques described in this book, readers are enabled to reduce the design effort through reuse of the same digital design instance, across a wide range of applications. All concepts the authors discuss are demonstrated by dedicated testchip designs and experimental results. To make the results immediately usable by the reader, all the scripts necessary to create automated design flows based on commercial tools are provided and explained. Provides extensive coverage of the challenges and the key technologies enabling wide power-performance range in digital sub-systems (e.g., processors, memories, accelerators); Includes in-depth description of silicon-proven methodologies to design reconfigurable data path and clock path; Describes techniques for reconfigurable microarchitectures, down to the pipestage and the clock repeater level; Uses a highly interdisciplinary approach covering the circuit, the microarchitectural and the system levels of abstraction; Presents practical design examples and the related methodologies; Offers complementary design files and scripts, useful to replicate the presented developments and develop new designs.
650 0 $a Digital electronics. $3 584066
650 1 4 $a Circuits and Systems. $3 896527
650 2 4 $a Cyber-physical systems, IoT. $3 3386699
650 2 4 $a Processor Architectures. $3 892680
700 1 $a Lin, Longyang. $3 3448549
700 1 $a Alioto, Massimo. $3 896604
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer eBooks
856 4 0 $u https://doi.org/10.1007/978-3-030-38796-9
950 $a Engineering (Springer-11647)