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Model and design of improved current...

Gupta, Kirti.

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Model and design of improved current mode logic gates = differential and single-ended /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Model and design of improved current mode logic gates/ by Kirti Gupta, Neeta Pandey, Maneesha Gupta.
Reminder of title:	differential and single-ended /
Author:	Gupta, Kirti.
other author:	Pandey, Neeta.
Published:	Singapore :Springer Singapore : : 2020.,
Description:	xiv, 171 p. :ill., digital ;24 cm.
[NT 15003449]:	Introduction -- Current Mode Logic (CML): Basic concepts -- Differential CML Gates with Modified PDN -- CML Gates with Modified Current Source -- CML Gates with Modified Load -- PFSCL Circuits with Reduced Gate Count -- Tri-State CML Circuits.
Contained By:	Springer eBooks
Subject:	Metal oxide semiconductor field-effect transistors. -
Online resource:	https://doi.org/10.1007/978-981-15-0982-7
ISBN:	9789811509827

Model and design of improved current mode logic gates = differential and single-ended /
Gupta, Kirti.

Model and design of improved current mode logic gatesdifferential and single-ended /[electronic resource] :by Kirti Gupta, Neeta Pandey, Maneesha Gupta. - Singapore :Springer Singapore :2020. - xiv, 171 p. :ill., digital ;24 cm.

Introduction -- Current Mode Logic (CML): Basic concepts -- Differential CML Gates with Modified PDN -- CML Gates with Modified Current Source -- CML Gates with Modified Load -- PFSCL Circuits with Reduced Gate Count -- Tri-State CML Circuits.

This book presents MOSFET-based current mode logic (CML) topologies, which increase the speed, and lower the transistor count, supply voltage and power consumption. The improved topologies modify the conventional PDN, load, and the current source sections of the basic CML gates. Electronic system implementation involves embedding digital and analog circuits on a single die shifting towards mixed-mode circuit design. The high-resolution, low-power and low-voltage analog circuits are combined with high-frequency complex digital circuits, and the conventional static CMOS logic generates large current spikes during the switching (also referred to as digital switching noise), which degrade the resolution of the sensitive analog circuits via supply line and substrate coupling. This problem is exacerbated further with scaling down of CMOS technology due to higher integration levels and operating frequencies. In the literature, several methods are described to reduce the propagation of the digital switching noise. However, in high-resolution applications, these methods are not sufficient. The conventional CMOS static logic is no longer an effective solution, and therefore an alternative with reduced current spikes or that draws a constant supply current must be selected. The current mode logic (CML) topology, with its unique property of requiring constant supply current, is a promising alternative to the conventional CMOS static logic.

ISBN: 9789811509827

Standard No.: 10.1007/978-981-15-0982-7doiSubjects--Topical Terms:

553297
Metal oxide semiconductor field-effect transistors.

LC Class. No.: TK7871.99.M44 / G86 2020

Dewey Class. No.: 004.6

Model and design of improved current mode logic gates = differential and single-ended /
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245 1 0 $a Model and design of improved current mode logic gates $h [electronic resource] : $b differential and single-ended / $c by Kirti Gupta, Neeta Pandey, Maneesha Gupta.
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300 $a xiv, 171 p. : $b ill., digital ; $c 24 cm.
505 0 $a Introduction -- Current Mode Logic (CML): Basic concepts -- Differential CML Gates with Modified PDN -- CML Gates with Modified Current Source -- CML Gates with Modified Load -- PFSCL Circuits with Reduced Gate Count -- Tri-State CML Circuits.
520 $a This book presents MOSFET-based current mode logic (CML) topologies, which increase the speed, and lower the transistor count, supply voltage and power consumption. The improved topologies modify the conventional PDN, load, and the current source sections of the basic CML gates. Electronic system implementation involves embedding digital and analog circuits on a single die shifting towards mixed-mode circuit design. The high-resolution, low-power and low-voltage analog circuits are combined with high-frequency complex digital circuits, and the conventional static CMOS logic generates large current spikes during the switching (also referred to as digital switching noise), which degrade the resolution of the sensitive analog circuits via supply line and substrate coupling. This problem is exacerbated further with scaling down of CMOS technology due to higher integration levels and operating frequencies. In the literature, several methods are described to reduce the propagation of the digital switching noise. However, in high-resolution applications, these methods are not sufficient. The conventional CMOS static logic is no longer an effective solution, and therefore an alternative with reduced current spikes or that draws a constant supply current must be selected. The current mode logic (CML) topology, with its unique property of requiring constant supply current, is a promising alternative to the conventional CMOS static logic.
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700 1 $a Gupta, Maneesha. $3 3445131
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