東華大學圖書館 |

Language: English

Help

回圖書館首頁

手機版館藏查詢

Back

Switch To: Labeled | MARC Mode | ISBD

FPGA-BASED hardware accelerators

Skliarova, Iouliia.

Linked to FindBook

Google Book

Amazon

博客來

FPGA-BASED hardware accelerators

Record Type:	Electronic resources : Monograph/item
Title/Author:	FPGA-BASED hardware accelerators/ by Iouliia Skliarova, Valery Sklyarov.
Author:	Skliarova, Iouliia.
other author:	Sklyarov, Valery.
Published:	Cham :Springer International Publishing : : 2019.,
Description:	xvi, 245 p. :ill., digital ;24 cm.
[NT 15003449]:	Reconfigurable devices and design tools -- Architectures of FPGA-based hardware accelerators and design techniques -- Hardware accelerators for data search -- Hardware accelerators for data sort -- FPGA-based hardware accelerators for selected computational problems -- Hardware/software co-design.
Contained By:	Springer eBooks
Subject:	Field programmable gate arrays. -
Online resource:	https://doi.org/10.1007/978-3-030-20721-2
ISBN:	9783030207212

FPGA-BASED hardware accelerators
Skliarova, Iouliia.

FPGA-BASED hardware accelerators[electronic resource] /by Iouliia Skliarova, Valery Sklyarov. - Cham :Springer International Publishing :2019. - xvi, 245 p. :ill., digital ;24 cm. - Lecture notes in electrical engineering,v.5661876-1100 ;. - Lecture notes in electrical engineering ;v.566..

Reconfigurable devices and design tools -- Architectures of FPGA-based hardware accelerators and design techniques -- Hardware accelerators for data search -- Hardware accelerators for data sort -- FPGA-based hardware accelerators for selected computational problems -- Hardware/software co-design.

This book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design.

ISBN: 9783030207212

Standard No.: 10.1007/978-3-030-20721-2doiSubjects--Topical Terms:

666370
Field programmable gate arrays.

LC Class. No.: TK7895.G36 / S555 2019

Dewey Class. No.: 621.395

FPGA-BASED hardware accelerators
LDR:03004nmm a2200337 a 4500 001 2191409
003 DE-He213
005 20191028094855.0
006 m d
007 cr nn 008maaau
008 200504s2019 gw s 0 eng d
020 $a 9783030207212 $q (electronic bk.)
020 $a 9783030207205 $q (paper)
024 7 $a 10.1007/978-3-030-20721-2 $2 doi
035 $a 978-3-030-20721-2
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7895.G36 $b S555 2019
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.395 $2 23
090 $a TK7895.G36 $b S628 2019
100 1 $a Skliarova, Iouliia. $3 3410751
245 1 0 $a FPGA-BASED hardware accelerators $h [electronic resource] / $c by Iouliia Skliarova, Valery Sklyarov.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2019.
300 $a xvi, 245 p. : $b ill., digital ; $c 24 cm.
490 1 $a Lecture notes in electrical engineering, $x 1876-1100 ; $v v.566
505 0 $a Reconfigurable devices and design tools -- Architectures of FPGA-based hardware accelerators and design techniques -- Hardware accelerators for data search -- Hardware accelerators for data sort -- FPGA-based hardware accelerators for selected computational problems -- Hardware/software co-design.
520 $a This book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design.
650 0 $a Field programmable gate arrays. $3 666370
650 1 4 $a Circuits and Systems. $3 896527
650 2 4 $a Computational Intelligence. $3 1001631
700 1 $a Sklyarov, Valery. $3 2059351
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer eBooks
830 0 $a Lecture notes in electrical engineering ; $v v.566. $3 3410752
856 4 0 $u https://doi.org/10.1007/978-3-030-20721-2
950 $a Engineering (Springer-11647)