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Modeling, synthesis, and rapid proto...

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Ciletti, Michael D.

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Modeling, synthesis, and rapid prototyping with the Verilog HDL /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Modeling, synthesis, and rapid prototyping with the Verilog HDL // Michael D. Ciletti.
Author:	Ciletti, Michael D.
Published:	Upper Saddle River, N.J. :Prentice Hall, : c1999.,
Description:	xxii, 727 p. :ill. ;25 cm.
Subject:	Verilog (Computer hardware description language). -
ISBN:	0139773983 (pbk.) :

Modeling, synthesis, and rapid prototyping with the Verilog HDL /
Ciletti, Michael D.

Modeling, synthesis, and rapid prototyping with the Verilog HDL /Michael D. Ciletti. - Upper Saddle River, N.J. :Prentice Hall,c1999. - xxii, 727 p. :ill. ;25 cm.

Includes bibliographical references and index.

ISBN: 0139773983 (pbk.) :NT4012

LCCN: 99010494Subjects--Topical Terms:

750071
Verilog (Computer hardware description language).

LC Class. No.: TK7885.7 / .C55 1999

Dewey Class. No.: 621.392

Modeling, synthesis, and rapid prototyping with the Verilog HDL /
LDR:00586cam 2200181 a 4500 001 2188548
005 20071211170027.0
008 200310s1999 njua b 001 0 eng
010 $a 99010494
020 $a 0139773983 (pbk.) : $c NT4012
035 $a 00994917
040 $a DLC $c DLC $d WaU $d NCTU
042 $a pcc
050 0 0 $a TK7885.7 $b .C55 1999
082 0 0 $a 621.392 $2 21
100 1 $a Ciletti, Michael D. $3 1048021
245 1 0 $a Modeling, synthesis, and rapid prototyping with the Verilog HDL / $c Michael D. Ciletti.
260 # $a Upper Saddle River, N.J. : $b Prentice Hall, $c c1999.
300 $a xxii, 727 p. : $b ill. ; $c 25 cm.
504 $a Includes bibliographical references and index.
650 # 0 $a Verilog (Computer hardware description language). $3 750071
650 # 0 $a Rapid prototyping. $3 820011

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六樓西文書區HC-Z(6F Western Language Books)

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TK7885.7 C55 1999

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