東華大學圖書館 |

Language: English

Help

回圖書館首頁

手機版館藏查詢

Back

Switch To: Labeled | MARC Mode | ISBD

Advanced HDL synthesis and SOC proto...

Taraate, Vaibbhav.

Linked to FindBook

Google Book

Amazon

博客來

Advanced HDL synthesis and SOC prototyping = RTL design using verilog /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Advanced HDL synthesis and SOC prototyping/ by Vaibbhav Taraate.
Reminder of title:	RTL design using verilog /
Author:	Taraate, Vaibbhav.
Published:	Singapore :Springer Singapore : : 2019.,
Description:	xxi, 307 p. :ill., digital ;24 cm.
[NT 15003449]:	Introduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level.
Contained By:	Springer eBooks
Subject:	Systems on a chip. -
Online resource:	https://doi.org/10.1007/978-981-10-8776-9
ISBN:	9789811087769

Advanced HDL synthesis and SOC prototyping = RTL design using verilog /
Taraate, Vaibbhav.

Advanced HDL synthesis and SOC prototypingRTL design using verilog /[electronic resource] :by Vaibbhav Taraate. - Singapore :Springer Singapore :2019. - xxi, 307 p. :ill., digital ;24 cm.

Introduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level.

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.

ISBN: 9789811087769

Standard No.: 10.1007/978-981-10-8776-9doiSubjects--Topical Terms:

729732
Systems on a chip.

LC Class. No.: TK7895.E42 / T373 2019

Dewey Class. No.: 621.3815

Advanced HDL synthesis and SOC prototyping = RTL design using verilog /
LDR:02352nmm a2200325 a 4500 001 2178701
003 DE-He213
005 20190704100022.0
006 m d
007 cr nn 008maaau
008 191122s2019 si s 0 eng d
020 $a 9789811087769 $q (electronic bk.)
020 $a 9789811087752 $q (paper)
024 7 $a 10.1007/978-981-10-8776-9 $2 doi
035 $a 978-981-10-8776-9
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7895.E42 $b T373 2019
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
090 $a TK7895.E42 $b T176 2019
100 1 $a Taraate, Vaibbhav. $3 2195158
245 1 0 $a Advanced HDL synthesis and SOC prototyping $h [electronic resource] : $b RTL design using verilog / $c by Vaibbhav Taraate.
260 $a Singapore : $b Springer Singapore : $b Imprint: Springer, $c 2019.
300 $a xxi, 307 p. : $b ill., digital ; $c 24 cm.
505 0 $a Introduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level.
520 $a This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.
650 0 $a Systems on a chip. $3 729732
650 0 $a Verilog (Computer hardware description language) $3 709274
650 1 4 $a Circuits and Systems. $3 896527
650 2 4 $a Control Structures and Microprogramming. $3 895886
650 2 4 $a Logic Design. $3 892735
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer eBooks
856 4 0 $u https://doi.org/10.1007/978-981-10-8776-9
950 $a Engineering (Springer-11647)