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Post-silicon validation and debug

Mishra, Prabhat.

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Post-silicon validation and debug

Record Type:	Electronic resources : Monograph/item
Title/Author:	Post-silicon validation and debug/ edited by Prabhat Mishra, Farimah Farahmandi.
other author:	Mishra, Prabhat.
Published:	Cham :Springer International Publishing : : 2019.,
Description:	xv, 394 p. :ill., digital ;24 cm.
[NT 15003449]:	Part 1. Introduction -- Post-Silicon SoC Validation Challenges -- Part 2. Debug Infrastructure -- SoC Instrumentations: Pre-silicon Preparation for Post-silicon Readiness -- Structure-based Signal Selection for Post-silicon Validation -- Simulation-based Signal Selection -- Hybrid Signal Selection -- Post-Silicon Signal Selection using Machine Learning -- Part 3. Generation of Tests and Assertions -- Observability-aware Post-Silicon Test Generation -- On-chip Constrained-Random Stimuli Generation -- Test Generation and Lightweight Checking for Multi-core Memory Consistency -- Selection of Post-Silicon Hardware Assertions -- Part 4. Post-Silicon Debug -- Debug Data Reduction Techniques -- High-level Debugging of Post-silicon Failures -- Post-silicon Fault Localization with Satisfiability Solvers -- Coverage Evaluation and Analysis of Post-silicon Tests with Virtual Prototypes -- Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis -- Part 5. Case Studies -- Network-on-Chip Validation and Debug -- Post-silicon Validation of the IBM Power8 Processor -- Part 6. Conclusion and Future Directions -- SoC Security versus Post-Silicon Debug Conflict -- The Future of Post-Silicon Debug.
Contained By:	Springer eBooks
Subject:	Debugging in computer science. -
Online resource:	https://doi.org/10.1007/978-3-319-98116-1
ISBN:	9783319981161

Post-silicon validation and debug
Post-silicon validation and debug[electronic resource] /edited by Prabhat Mishra, Farimah Farahmandi. - Cham :Springer International Publishing :2019. - xv, 394 p. :ill., digital ;24 cm.

Part 1. Introduction -- Post-Silicon SoC Validation Challenges -- Part 2. Debug Infrastructure -- SoC Instrumentations: Pre-silicon Preparation for Post-silicon Readiness -- Structure-based Signal Selection for Post-silicon Validation -- Simulation-based Signal Selection -- Hybrid Signal Selection -- Post-Silicon Signal Selection using Machine Learning -- Part 3. Generation of Tests and Assertions -- Observability-aware Post-Silicon Test Generation -- On-chip Constrained-Random Stimuli Generation -- Test Generation and Lightweight Checking for Multi-core Memory Consistency -- Selection of Post-Silicon Hardware Assertions -- Part 4. Post-Silicon Debug -- Debug Data Reduction Techniques -- High-level Debugging of Post-silicon Failures -- Post-silicon Fault Localization with Satisfiability Solvers -- Coverage Evaluation and Analysis of Post-silicon Tests with Virtual Prototypes -- Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis -- Part 5. Case Studies -- Network-on-Chip Validation and Debug -- Post-silicon Validation of the IBM Power8 Processor -- Part 6. Conclusion and Future Directions -- SoC Security versus Post-Silicon Debug Conflict -- The Future of Post-Silicon Debug.

This book provides a comprehensive coverage of System-on-Chip (SoC) post-silicon validation and debug challenges and state-of-the-art solutions with contributions from SoC designers, academic researchers as well as SoC verification experts. The readers will get a clear understanding of the existing debug infrastructure and how they can be effectively utilized to verify and debug SoCs. Provides a comprehensive overview of the SoC post-silicon validation and debug challenges; Covers state-of-the-art techniques for developing on-chip debug infrastructure; Describes automated techniques for generating post-silicon tests and assertions to enable effective post-silicon debug and coverage analysis; Covers scalable post-silicon validation and bug localization using a combination of simulation-based techniques and formal methods; Presents case studies for post-silicon debug of industrial SoC designs.

ISBN: 9783319981161

Standard No.: 10.1007/978-3-319-98116-1doiSubjects--Topical Terms:

590474
Debugging in computer science.

LC Class. No.: QA76.9.D43

Dewey Class. No.: 004.24

Post-silicon validation and debug
LDR:03073nmm a2200325 a 4500 001 2176951
003 DE-He213
005 20180903021034.0
006 m d
007 cr nn 008maaau
008 191122s2019 gw s 0 eng d
020 $a 9783319981161 $q (electronic bk.)
020 $a 9783319981154 $q (paper)
024 7 $a 10.1007/978-3-319-98116-1 $2 doi
035 $a 978-3-319-98116-1
040 $a GP $c GP
041 0 $a eng
050 4 $a QA76.9.D43
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 004.24 $2 23
090 $a QA76.9.D43 $b P857 2019
245 0 0 $a Post-silicon validation and debug $h [electronic resource] / $c edited by Prabhat Mishra, Farimah Farahmandi.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2019.
300 $a xv, 394 p. : $b ill., digital ; $c 24 cm.
505 0 $a Part 1. Introduction -- Post-Silicon SoC Validation Challenges -- Part 2. Debug Infrastructure -- SoC Instrumentations: Pre-silicon Preparation for Post-silicon Readiness -- Structure-based Signal Selection for Post-silicon Validation -- Simulation-based Signal Selection -- Hybrid Signal Selection -- Post-Silicon Signal Selection using Machine Learning -- Part 3. Generation of Tests and Assertions -- Observability-aware Post-Silicon Test Generation -- On-chip Constrained-Random Stimuli Generation -- Test Generation and Lightweight Checking for Multi-core Memory Consistency -- Selection of Post-Silicon Hardware Assertions -- Part 4. Post-Silicon Debug -- Debug Data Reduction Techniques -- High-level Debugging of Post-silicon Failures -- Post-silicon Fault Localization with Satisfiability Solvers -- Coverage Evaluation and Analysis of Post-silicon Tests with Virtual Prototypes -- Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis -- Part 5. Case Studies -- Network-on-Chip Validation and Debug -- Post-silicon Validation of the IBM Power8 Processor -- Part 6. Conclusion and Future Directions -- SoC Security versus Post-Silicon Debug Conflict -- The Future of Post-Silicon Debug.
520 $a This book provides a comprehensive coverage of System-on-Chip (SoC) post-silicon validation and debug challenges and state-of-the-art solutions with contributions from SoC designers, academic researchers as well as SoC verification experts. The readers will get a clear understanding of the existing debug infrastructure and how they can be effectively utilized to verify and debug SoCs. Provides a comprehensive overview of the SoC post-silicon validation and debug challenges; Covers state-of-the-art techniques for developing on-chip debug infrastructure; Describes automated techniques for generating post-silicon tests and assertions to enable effective post-silicon debug and coverage analysis; Covers scalable post-silicon validation and bug localization using a combination of simulation-based techniques and formal methods; Presents case studies for post-silicon debug of industrial SoC designs.
650 0 $a Debugging in computer science. $3 590474
650 1 4 $a Circuits and Systems. $3 896527
650 2 4 $a Processor Architectures. $3 892680
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 893838
700 1 $a Mishra, Prabhat. $3 896585
700 1 $a Farahmandi, Farimah. $3 3379530
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer eBooks
856 4 0 $u https://doi.org/10.1007/978-3-319-98116-1
950 $a Engineering (Springer-11647)