東華大學圖書館 |

Language: English

Help

回圖書館首頁

手機版館藏查詢

Back

Switch To: Labeled | MARC Mode | ISBD

COMMSYN: On -chip communication arch...

Pasricha, Sudeep.

Linked to FindBook

Google Book

Amazon

博客來

COMMSYN: On -chip communication architecture synthesis for Multi-Processor Systems-on-Chip.

Record Type:	Electronic resources : Monograph/item
Title/Author:	COMMSYN: On -chip communication architecture synthesis for Multi-Processor Systems-on-Chip./
Author:	Pasricha, Sudeep.
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2008,
Description:	206 p.
Notes:	Source: Dissertation Abstracts International, Volume: 69-06, Section: B, page: 3666.
Contained By:	Dissertation Abstracts International69-06B.
Subject:	Computer science. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3318721
ISBN:	9780549682110

COMMSYN: On -chip communication architecture synthesis for Multi-Processor Systems-on-Chip.
Pasricha, Sudeep.

COMMSYN: On -chip communication architecture synthesis for Multi-Processor Systems-on-Chip. - Ann Arbor : ProQuest Dissertations & Theses, 2008 - 206 p.

Source: Dissertation Abstracts International, Volume: 69-06, Section: B, page: 3666.

Thesis (Ph.D.)--University of California, Irvine, 2008.

With the increasing performance demands of emerging convergence applications and advances in process technology, Multiprocessor Systems-on-Chip (MPSoCs) are becoming prevalent in modern embedded systems. The on-chip communication architecture that interconnects the various components in such systems has a large and critical impact on the overall system performance, power, cost and reliability. Consequently, the design, exploration and implementation of on-chip communication architectures have become some of the most time-consuming activities for system designers in a typical MPSoC design flow. The task of on-chip communication architecture design is further hampered by a lack of state-of-the-art system-level tools and methodologies to cope with their increasingly significant role in systems today.

ISBN: 9780549682110Subjects--Topical Terms:

523869
Computer science.

COMMSYN: On -chip communication architecture synthesis for Multi-Processor Systems-on-Chip.
LDR:02845nmm a2200301 4500 001 2161441
005 20180907134544.5
008 190424s2008 ||||||||||||||||| ||eng d
020 $a 9780549682110
035 $a (MiAaPQ)AAI3318721
035 $a AAI3318721
040 $a MiAaPQ $c MiAaPQ
100 1 $a Pasricha, Sudeep. $3 1000595
245 1 0 $a COMMSYN: On -chip communication architecture synthesis for Multi-Processor Systems-on-Chip.
260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2008
300 $a 206 p.
500 $a Source: Dissertation Abstracts International, Volume: 69-06, Section: B, page: 3666.
500 $a Adviser: Nikil Dutt.
502 $a Thesis (Ph.D.)--University of California, Irvine, 2008.
520 $a With the increasing performance demands of emerging convergence applications and advances in process technology, Multiprocessor Systems-on-Chip (MPSoCs) are becoming prevalent in modern embedded systems. The on-chip communication architecture that interconnects the various components in such systems has a large and critical impact on the overall system performance, power, cost and reliability. Consequently, the design, exploration and implementation of on-chip communication architectures have become some of the most time-consuming activities for system designers in a typical MPSoC design flow. The task of on-chip communication architecture design is further hampered by a lack of state-of-the-art system-level tools and methodologies to cope with their increasingly significant role in systems today.
520 $a In this dissertation, we propose the COMMSYN framework for automated exploration and synthesis of on-chip communication architectures in emerging heterogeneous MPSoC applications. We have developed fast and accurate simulation and power estimation models for reliable on-chip communication architecture exploration early in the design flow. These models are used in our framework to make informed decisions during synthesis. COMMSYN enables a physical-implementation-aware and memory-architecture-aware on-chip communication architecture synthesis, comprehensively and automatically generating both the topology and protocol parameters, while trading off multiple design constraints such as power, performance, area and cost.
520 $a Such a multi-faceted synthesis framework accrues many benefits for MPSoC designs such as improved design reliability and quality, better complexity management, reduced system cost and a faster time-to-market. The experiments on several industrial strength applications demonstrate the utility of the automated and comprehensive synthesis framework for MPSoC designs.
590 $a School code: 0030.
650 4 $a Computer science. $3 523869
690 $a 0984
710 2 $a University of California, Irvine. $3 705821
773 0 $t Dissertation Abstracts International $g 69-06B.
790 $a 0030
791 $a Ph.D.
792 $a 2008
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3318721