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Paving the Path for Heterogeneous Me...

Agarwal, Neha.

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Paving the Path for Heterogeneous Memory Adoption in Production Systems.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Paving the Path for Heterogeneous Memory Adoption in Production Systems./
Author:	Agarwal, Neha.
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2017,
Description:	148 p.
Notes:	Source: Dissertation Abstracts International, Volume: 78-11(E), Section: B.
Contained By:	Dissertation Abstracts International78-11B(E).
Subject:	Computer engineering. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10612063
ISBN:	9781369901979

Paving the Path for Heterogeneous Memory Adoption in Production Systems.
Agarwal, Neha.

Paving the Path for Heterogeneous Memory Adoption in Production Systems. - Ann Arbor : ProQuest Dissertations & Theses, 2017 - 148 p.

Source: Dissertation Abstracts International, Volume: 78-11(E), Section: B.

Thesis (Ph.D.)--University of Michigan, 2017.

Systems from smartphones to data-centers to supercomputers are increasingly heterogeneous, comprising various memory technologies and core types. Heterogeneous memory systems provide an opportunity to suitably match varying memory access patterns in applications, reducing CPU time thus increasing performance per dollar resulting in aggregate savings of millions of dollars in large-scale systems. However, with increased provisioning of main memory capacity per machine and differences in memory characteristics (for example, bandwidth, latency, cost, and density), memory management in such heterogeneous memory systems poses multi-fold challenges on system programmability and design.

ISBN: 9781369901979Subjects--Topical Terms:

621879
Computer engineering.

Paving the Path for Heterogeneous Memory Adoption in Production Systems.
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245 1 0 $a Paving the Path for Heterogeneous Memory Adoption in Production Systems.
260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2017
300 $a 148 p.
500 $a Source: Dissertation Abstracts International, Volume: 78-11(E), Section: B.
500 $a Adviser: Thomas F Wenisch.
502 $a Thesis (Ph.D.)--University of Michigan, 2017.
520 $a Systems from smartphones to data-centers to supercomputers are increasingly heterogeneous, comprising various memory technologies and core types. Heterogeneous memory systems provide an opportunity to suitably match varying memory access patterns in applications, reducing CPU time thus increasing performance per dollar resulting in aggregate savings of millions of dollars in large-scale systems. However, with increased provisioning of main memory capacity per machine and differences in memory characteristics (for example, bandwidth, latency, cost, and density), memory management in such heterogeneous memory systems poses multi-fold challenges on system programmability and design.
520 $a In this thesis, we tackle memory management of two heterogeneous memory systems: (a) CPU-GPU systems with a unified virtual address space, and (b) Cloud computing platforms that can deploy cheaper but slower memory technologies alongside DRAMs to reduce cost of memory in data-centers. First, we show that operating systems do not have sufficient information to optimally manage pages in bandwidth-asymmetric systems and thus fail to maximize bandwidth to massively-threaded GPU applications sacrificing GPU throughput. We present BW-AWARE placement/migration policies to support OS to make optimal data management decisions. Second, we present a CPU-GPU cache coherence design where CPU and GPU need not implement same cache coherence protocol but provide cache-coherent memory interface to the programmer. Our proposal is first practical approach to provide a unified, coherent CPU--GPU address space without requiring hardware cache coherence, with a potential to enable an explosion in algorithms that leverage tightly coupled CPU--GPU coordination.
520 $a Finally, to reduce the cost of memory in cloud platforms where the trend has been to map datasets in memory, we make a case for a two-tiered memory system where cheaper (per bit) memories, such as Intel/Microns 3D XPoint, will be deployed alongside DRAM. We present Thermostat, an application-transparent huge-page-aware software mechanism to place pages in a dual-technology hybrid memory system while achieving both the cost advantages of two-tiered memory and performance advantages of transparent huge pages. With Thermostat's capability to control the application slowdown on a per application basis, cloud providers can realize cost savings from upcoming cheaper memory technologies by shifting infrequently accessed cold data to slow memory, while satisfying throughput demand of the customers.
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