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Fan-out wafer-level packaging

Lau, John H.

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Fan-out wafer-level packaging

Record Type:	Electronic resources : Monograph/item
Title/Author:	Fan-out wafer-level packaging/ by John H. Lau.
Author:	Lau, John H.
Published:	Singapore :Springer Singapore : : 2018.,
Description:	xx, 303 p. :ill. (some col.), digital ;24 cm.
[NT 15003449]:	Patent Issues of Fan-out Wafer-Level Packaging -- Flip Chip Technology vs. FOWLP -- Fan-In Wafer-Level Packaging vs. FOWLP -- Embedded Chip Packaging -- FOWLP: Chip-First and Die Face-Down -- FOWLP: Chip-First and Die Face-Up -- FOWLP: Chip-Last or RDL-First -- FOWLP: PoP with FOWLP -- Fan-Out Panel-Level Packaging (FOPLP) -- 3D Integration -- Heterogeneous Integration.
Contained By:	Springer eBooks
Subject:	Chip scale packaging. -
Online resource:	http://dx.doi.org/10.1007/978-981-10-8884-1
ISBN:	9789811088841

Fan-out wafer-level packaging
Lau, John H.

Fan-out wafer-level packaging[electronic resource] /by John H. Lau. - Singapore :Springer Singapore :2018. - xx, 303 p. :ill. (some col.), digital ;24 cm.

Patent Issues of Fan-out Wafer-Level Packaging -- Flip Chip Technology vs. FOWLP -- Fan-In Wafer-Level Packaging vs. FOWLP -- Embedded Chip Packaging -- FOWLP: Chip-First and Die Face-Down -- FOWLP: Chip-First and Die Face-Up -- FOWLP: Chip-Last or RDL-First -- FOWLP: PoP with FOWLP -- Fan-Out Panel-Level Packaging (FOPLP) -- 3D Integration -- Heterogeneous Integration.

This comprehensive guide to fan-out wafer-level packaging (FOWLP) technology compares FOWLP with flip chip and fan-in wafer-level packaging. It presents the current knowledge on these key enabling technologies for FOWLP, and discusses several packaging technologies for future trends. The Taiwan Semiconductor Manufacturing Company (TSMC) employed their InFO (integrated fan-out) technology in A10, the application processor for Apple's iPhone, in 2016, generating great excitement about FOWLP technology throughout the semiconductor packaging community. For many practicing engineers and managers, as well as scientists and researchers, essential details of FOWLP - such as the temporary bonding and de-bonding of the carrier on a reconstituted wafer/panel, epoxy molding compound (EMC) dispensing, compression molding, Cu revealing, RDL fabrication, solder ball mounting, etc. - are not well understood. Intended to help readers learn the basics of problem-solving methods and understand the trade-offs inherent in making system-level decisions quickly, this book serves as a valuable reference guide for all those faced with the challenging problems created by the ever-increasing interest in FOWLP, helps to remove roadblocks, and accelerates the design, materials, process, and manufacturing development of key enabling technologies for FOWLP.

ISBN: 9789811088841

Standard No.: 10.1007/978-981-10-8884-1doiSubjects--Topical Terms:

2132927
Chip scale packaging.

LC Class. No.: TK7870.17 / .L385 2018

Dewey Class. No.: 621.381046

Fan-out wafer-level packaging
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100 1 $a Lau, John H. $3 858903
245 1 0 $a Fan-out wafer-level packaging $h [electronic resource] / $c by John H. Lau.
260 $a Singapore : $b Springer Singapore : $b Imprint: Springer, $c 2018.
300 $a xx, 303 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Patent Issues of Fan-out Wafer-Level Packaging -- Flip Chip Technology vs. FOWLP -- Fan-In Wafer-Level Packaging vs. FOWLP -- Embedded Chip Packaging -- FOWLP: Chip-First and Die Face-Down -- FOWLP: Chip-First and Die Face-Up -- FOWLP: Chip-Last or RDL-First -- FOWLP: PoP with FOWLP -- Fan-Out Panel-Level Packaging (FOPLP) -- 3D Integration -- Heterogeneous Integration.
520 $a This comprehensive guide to fan-out wafer-level packaging (FOWLP) technology compares FOWLP with flip chip and fan-in wafer-level packaging. It presents the current knowledge on these key enabling technologies for FOWLP, and discusses several packaging technologies for future trends. The Taiwan Semiconductor Manufacturing Company (TSMC) employed their InFO (integrated fan-out) technology in A10, the application processor for Apple's iPhone, in 2016, generating great excitement about FOWLP technology throughout the semiconductor packaging community. For many practicing engineers and managers, as well as scientists and researchers, essential details of FOWLP - such as the temporary bonding and de-bonding of the carrier on a reconstituted wafer/panel, epoxy molding compound (EMC) dispensing, compression molding, Cu revealing, RDL fabrication, solder ball mounting, etc. - are not well understood. Intended to help readers learn the basics of problem-solving methods and understand the trade-offs inherent in making system-level decisions quickly, this book serves as a valuable reference guide for all those faced with the challenging problems created by the ever-increasing interest in FOWLP, helps to remove roadblocks, and accelerates the design, materials, process, and manufacturing development of key enabling technologies for FOWLP.
650 0 $a Chip scale packaging. $3 2132927
650 1 4 $a Engineering. $3 586835
650 2 4 $a Circuits and Systems. $3 896527
650 2 4 $a Nanotechnology and Microengineering. $3 1005737
650 2 4 $a Optical and Electronic Materials. $3 891120
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856 4 0 $u http://dx.doi.org/10.1007/978-981-10-8884-1
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