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Improving reliability and performanc...

Guo, Jie.

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Improving reliability and performance of NAND flash based storage system.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Improving reliability and performance of NAND flash based storage system./
作者:	Guo, Jie.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2016,
面頁冊數:	124 p.
附註:	Source: Dissertation Abstracts International, Volume: 78-04(E), Section: B.
Contained By:	Dissertation Abstracts International78-04B(E).
標題:	Computer engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10183714
ISBN:	9781369318388

Improving reliability and performance of NAND flash based storage system.
Guo, Jie.

Improving reliability and performance of NAND flash based storage system. - Ann Arbor : ProQuest Dissertations & Theses, 2016 - 124 p.

Source: Dissertation Abstracts International, Volume: 78-04(E), Section: B.

Thesis (Ph.D.)--University of Pittsburgh, 2016.

High seek and rotation overhead of magnetic hard disk drive (HDD) motivates development of storage devices, which can offer good random performance. As an alternative technology, NAND ash memory demonstrates low power consumption, microsecond-order access latency and good scalability. Thanks to these advantages, NAND ash based solid state disks (SSD) show many promising applications in enterprise servers. With multi-level cell (MLC) technique, the per-bit fabrication cost is reduced and low production cost enables NAND ash memory to extend its application to the consumer electronics.

ISBN: 9781369318388Subjects--Topical Terms:

621879
Computer engineering.

Improving reliability and performance of NAND flash based storage system.
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245 1 0 $a Improving reliability and performance of NAND flash based storage system.
260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2016
300 $a 124 p.
500 $a Source: Dissertation Abstracts International, Volume: 78-04(E), Section: B.
500 $a Adviser: Yiran Chen.
502 $a Thesis (Ph.D.)--University of Pittsburgh, 2016.
520 $a High seek and rotation overhead of magnetic hard disk drive (HDD) motivates development of storage devices, which can offer good random performance. As an alternative technology, NAND ash memory demonstrates low power consumption, microsecond-order access latency and good scalability. Thanks to these advantages, NAND ash based solid state disks (SSD) show many promising applications in enterprise servers. With multi-level cell (MLC) technique, the per-bit fabrication cost is reduced and low production cost enables NAND ash memory to extend its application to the consumer electronics.
520 $a Despite these advantages, limited memory endurance, long data protection latency and write amplification continue to be the major challenges in the designs of NAND ash storage systems. The limited memory endurance and long data protection latency issue derive from memory bit errors. High bit error rate (BER) severely impairs data integrity and reduces memory durance. The limited endurance is a major obstacle to apply NAND ash memory to the application with high reliability requirement. To protect data integrity, hard-decision error correction codes (ECC) such as Bose-Chaudhuri-Hocquenghem (BCH) are employed. However, the hardware cost becomes prohibitively with the increase of BER when the BCH ECC is employed to extend system lifetime. To extend system lifespan without high hardware cost, we has proposed data pattern aware (DPA) error prevention system design. DPA realizes BER reduction by minimizing the occurrence of data patterns vulnerable to high BER with simple linear feedback shift register circuits. Experimental results show that DPA can increase the system lifetime by up to 4x with marginal hardware cost.
520 $a With the technology node scaling down to 2Xnm, BER increases up to 10 -2. Hard-decision ECCs and DPA are no longer applicable to guarantee data integrity due to either prohibitively high hardware cost or high storage overhead. Soft-decision ECC, such as low-density parity-check (LDPC) code, has been introduced to provide more powerful error correction capability. However, LDPC code demands extra memory sensing operations, directly leading to long read latency. To reduce LDPC code induced read latency without adverse impact on system reliability, we has proposed FlexLevel NAND ash storage system design. The FlexLevel design reduces BER by broadening the noise margin via threshold voltage (Vth) level reduction. Under relatively low BER, no extra sensing level is required and therefore read performance can be improved. To balance Vth level reduction induced capacity loss and the read speedup, the FlexLevel design identifies the data with high LDPC overhead and only performs V th reduction to these data. Experimental results show that compared with the best existing works, the proposed design achieves up to 11% read speedup with negligible capacity loss.
520 $a Write amplification is a major cause to performance and endurance degradation of the NAND ash based storage system. In the object-based NAND ash device (ONFD), write amplification partially results from onode partial update and cascading update. Onode partial update only over-writes partial data of a NAND ash page and incurs unnecessary data migration of the un-updated data. Cascading update is update to object metadata in a cascading manner due to object data update or migration. Even through only several bytes in the object metadata are updated, one or more page has to be re-written, significantly degrading write performance. To minimize write operations incurred by onode partial update and cascading update, we has proposed a Data Migration Minimizing (DMM) device design. The DMM device incorporates 1) the multi-level garbage collection technique to minimize the unnecessary data migration of onode partial update and 2) the virtual B+ tree and diff cache to reduce the write operations incurred by cascading update. The experiment results demonstrate that the DMM device can offer up to 20% write reduction compared with the best state-of-art works.
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773 0 $t Dissertation Abstracts International $g 78-04B(E).
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