東華大學圖書館 |

Language: English

Help

回圖書館首頁

手機版館藏查詢

Back

Switch To: Labeled | MARC Mode | ISBD

From variability tolerance to approx...

Rahimi, Abbas.

Linked to FindBook

Google Book

Amazon

博客來

From variability tolerance to approximate computing in parallel integrated architectures and accelerators

Record Type:	Electronic resources : Monograph/item
Title/Author:	From variability tolerance to approximate computing in parallel integrated architectures and accelerators/ by Abbas Rahimi, Luca Benini, Rajesh K. Gupta.
Author:	Rahimi, Abbas.
other author:	Benini, Luca.
Published:	Cham :Springer International Publishing : : 2017.,
Description:	xv, 197 p. :ill. (some col.), digital ;24 cm.
[NT 15003449]:	Introduction -- Part 1. Predicting and Preventing Errors -- Instruction-Level Tolerance -- Sequence-Level Tolerance -- Procedure-Level Tolerance -- Kernel-Level Tolerance -- Hierarchically Focused Guardbanding -- Part 2. Detecting and Correcting Errors -- Work-Unit Tolerance -- Memristive-Based Associative Memory for Error Recovery -- Part 3. Accepting Errors -- Accuracy-Configurable OpenMP -- An Approximation Workflow for Exploiting Data-Level Parallelism in FPGA Acceleration -- Memristive-Based Associative Memory for Approximate Computational Reuse -- Spatial and Temporal Memoization -- Outlook.
Contained By:	Springer eBooks
Subject:	Computer architecture. -
Online resource:	http://dx.doi.org/10.1007/978-3-319-53768-9
ISBN:	9783319537689

From variability tolerance to approximate computing in parallel integrated architectures and accelerators
Rahimi, Abbas.

From variability tolerance to approximate computing in parallel integrated architectures and accelerators[electronic resource] /by Abbas Rahimi, Luca Benini, Rajesh K. Gupta. - Cham :Springer International Publishing :2017. - xv, 197 p. :ill. (some col.), digital ;24 cm.

Introduction -- Part 1. Predicting and Preventing Errors -- Instruction-Level Tolerance -- Sequence-Level Tolerance -- Procedure-Level Tolerance -- Kernel-Level Tolerance -- Hierarchically Focused Guardbanding -- Part 2. Detecting and Correcting Errors -- Work-Unit Tolerance -- Memristive-Based Associative Memory for Error Recovery -- Part 3. Accepting Errors -- Accuracy-Configurable OpenMP -- An Approximation Workflow for Exploiting Data-Level Parallelism in FPGA Acceleration -- Memristive-Based Associative Memory for Approximate Computational Reuse -- Spatial and Temporal Memoization -- Outlook.

ISBN: 9783319537689

Standard No.: 10.1007/978-3-319-53768-9doiSubjects--Topical Terms:

559837
Computer architecture.

LC Class. No.: QA76.9.A73

Dewey Class. No.: 004.22

From variability tolerance to approximate computing in parallel integrated architectures and accelerators
LDR:01603nmm a2200301 a 4500 001 2097553
003 DE-He213
005 20171103163025.0
006 m d
007 cr nn 008maaau
008 171229s2017 gw s 0 eng d
020 $a 9783319537689 $q (electronic bk.)
020 $a 9783319537672 $q (paper)
024 7 $a 10.1007/978-3-319-53768-9 $2 doi
035 $a 978-3-319-53768-9
040 $a GP $c GP
041 0 $a eng
050 4 $a QA76.9.A73
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 004.22 $2 23
090 $a QA76.9.A73 $b R147 2017
100 1 $a Rahimi, Abbas. $3 3236399
245 1 0 $a From variability tolerance to approximate computing in parallel integrated architectures and accelerators $h [electronic resource] / $c by Abbas Rahimi, Luca Benini, Rajesh K. Gupta.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2017.
300 $a xv, 197 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Introduction -- Part 1. Predicting and Preventing Errors -- Instruction-Level Tolerance -- Sequence-Level Tolerance -- Procedure-Level Tolerance -- Kernel-Level Tolerance -- Hierarchically Focused Guardbanding -- Part 2. Detecting and Correcting Errors -- Work-Unit Tolerance -- Memristive-Based Associative Memory for Error Recovery -- Part 3. Accepting Errors -- Accuracy-Configurable OpenMP -- An Approximation Workflow for Exploiting Data-Level Parallelism in FPGA Acceleration -- Memristive-Based Associative Memory for Approximate Computational Reuse -- Spatial and Temporal Memoization -- Outlook.
650 0 $a Computer architecture. $3 559837
650 0 $a Parallel processing (Electronic computers) $3 653284
650 1 4 $a Engineering. $3 586835
650 2 4 $a Circuits and Systems. $3 896527
650 2 4 $a Processor Architectures. $3 892680
650 2 4 $a Logic Design. $3 892735
700 1 $a Benini, Luca. $3 3236400
700 1 $a Gupta, Rajesh K. $3 3236401
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-53768-9
950 $a Engineering (Springer-11647)