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Automatic analog IC sizing and optim...

Lourenco, Nuno.

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Automatic analog IC sizing and optimization constrained with PVT corners and layout effects

Record Type:	Electronic resources : Monograph/item
Title/Author:	Automatic analog IC sizing and optimization constrained with PVT corners and layout effects/ by Nuno Lourenco, Ricardo Martins, Nuno Horta.
Author:	Lourenco, Nuno.
other author:	Martins, Ricardo.
Published:	Cham :Springer International Publishing : : 2017.,
Description:	xxvii, 182 p. :ill. (some col.), digital ;24 cm.
[NT 15003449]:	Introduction -- Previous Works on Automatic Analog IC Sizing -- AIDA-C Architecture -- Multi-Objective Optimization Kernel -- AIDA-C Circuit Sizing Results -- Layout-Aware Circuit Sizing -- AIDA-C Layout-aware Circuit Sizing Results -- Conclusions.
Contained By:	Springer eBooks
Subject:	Analog integrated circuits - Design. -
Online resource:	http://dx.doi.org/10.1007/978-3-319-42037-0
ISBN:	9783319420370

Automatic analog IC sizing and optimization constrained with PVT corners and layout effects
Lourenco, Nuno.

Automatic analog IC sizing and optimization constrained with PVT corners and layout effects[electronic resource] /by Nuno Lourenco, Ricardo Martins, Nuno Horta. - Cham :Springer International Publishing :2017. - xxvii, 182 p. :ill. (some col.), digital ;24 cm.

Introduction -- Previous Works on Automatic Analog IC Sizing -- AIDA-C Architecture -- Multi-Objective Optimization Kernel -- AIDA-C Circuit Sizing Results -- Layout-Aware Circuit Sizing -- AIDA-C Layout-aware Circuit Sizing Results -- Conclusions.

This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit's performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.

ISBN: 9783319420370

Standard No.: 10.1007/978-3-319-42037-0doiSubjects--Topical Terms:

2181209
Analog integrated circuits
--Design.

LC Class. No.: TK7874

Dewey Class. No.: 621.3815

Automatic analog IC sizing and optimization constrained with PVT corners and layout effects
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245 1 0 $a Automatic analog IC sizing and optimization constrained with PVT corners and layout effects $h [electronic resource] / $c by Nuno Lourenco, Ricardo Martins, Nuno Horta.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2017.
300 $a xxvii, 182 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Introduction -- Previous Works on Automatic Analog IC Sizing -- AIDA-C Architecture -- Multi-Objective Optimization Kernel -- AIDA-C Circuit Sizing Results -- Layout-Aware Circuit Sizing -- AIDA-C Layout-aware Circuit Sizing Results -- Conclusions.
520 $a This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit's performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.
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650 2 4 $a Processor Architectures. $3 892680
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 893838
700 1 $a Martins, Ricardo. $3 3216413
700 1 $a Horta, Nuno. $3 2134696
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