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Analysis and design of networks-on-c...

Ezz-Eldin, Rabab.

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Analysis and design of networks-on-chip under high process variation

Record Type:	Electronic resources : Monograph/item
Title/Author:	Analysis and design of networks-on-chip under high process variation/ by Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F.A. Hamed.
Author:	Ezz-Eldin, Rabab.
other author:	El-Moursy, Magdy Ali.
Published:	Cham :Springer International Publishing : : 2015.,
Description:	xxi, 141 p. :ill. (some col.), digital ;24 cm.
[NT 15003449]:	Introduction -- Network On Chip Aspects -- Interconnection -- Process Variation -- Synchronous And Asynchronous NoC Design Under High Process Variation -- Novel Routing Algorithm -- Simulation Results -- Conclusions.
Contained By:	Springer eBooks
Subject:	Networks on a chip - Design. -
Online resource:	http://dx.doi.org/10.1007/978-3-319-25766-2
ISBN:	9783319257662$q(electronic bk.)

Analysis and design of networks-on-chip under high process variation
Ezz-Eldin, Rabab.

Analysis and design of networks-on-chip under high process variation[electronic resource] /by Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F.A. Hamed. - Cham :Springer International Publishing :2015. - xxi, 141 p. :ill. (some col.), digital ;24 cm.

Introduction -- Network On Chip Aspects -- Interconnection -- Process Variation -- Synchronous And Asynchronous NoC Design Under High Process Variation -- Novel Routing Algorithm -- Simulation Results -- Conclusions.

This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns. Demonstrates the impact of process variation on Networks-on-Chip of different topologies; Includes an overview of the synchronous clocking scheme, clock distribution network, main building blocks in asynchronous NoC design, handshake protocols, data encoding, asynchronous protocol converters and routing algorithms; Describes a novel adaptive routing algorithm for asynchronous NoC designs, which selects the appr opriate output path based on process variation and congestion.

ISBN: 9783319257662$q(electronic bk.)

Standard No.: 10.1007/978-3-319-25766-2doiSubjects--Topical Terms:

2054658
Networks on a chip
--Design.

LC Class. No.: TK5105.546

Dewey Class. No.: 006.22

Analysis and design of networks-on-chip under high process variation
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100 1 $a Ezz-Eldin, Rabab. $3 2165564
245 1 0 $a Analysis and design of networks-on-chip under high process variation $h [electronic resource] / $c by Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F.A. Hamed.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2015.
300 $a xxi, 141 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Introduction -- Network On Chip Aspects -- Interconnection -- Process Variation -- Synchronous And Asynchronous NoC Design Under High Process Variation -- Novel Routing Algorithm -- Simulation Results -- Conclusions.
520 $a This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns. Demonstrates the impact of process variation on Networks-on-Chip of different topologies; Includes an overview of the synchronous clocking scheme, clock distribution network, main building blocks in asynchronous NoC design, handshake protocols, data encoding, asynchronous protocol converters and routing algorithms; Describes a novel adaptive routing algorithm for asynchronous NoC designs, which selects the appr opriate output path based on process variation and congestion.
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650 2 4 $a Circuits and Systems. $3 896527
650 2 4 $a Processor Architectures. $3 892680
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 893838
700 1 $a El-Moursy, Magdy Ali. $3 2165565
700 1 $a Hamed, Hesham F.A. $3 2165566
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