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Qu, Shichun.

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Wafer-level chip-scale packaging = analog and power semiconductor applications /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Wafer-level chip-scale packaging/ by Shichun Qu, Yong Liu.
Reminder of title:	analog and power semiconductor applications /
Author:	Qu, Shichun.
other author:	Liu, Yong.
Published:	New York, NY :Springer New York : : 2015.,
Description:	xvii, 322 p. :ill., digital ;24 cm.
[NT 15003449]:	Chapter 1. Demand and Challenges for Wafer Level Analog and Power Packaging -- Chapter 2. Fan-In Analog Wafer Level Chip Scale Package -- Chapter 3. Fan-Out Analog Wafer Level Chip Scale Package -- Chapter 4. Wafer Level Analog Chip Scale Package Stackable Design -- Chapter 5. Wafer Level Discrete Power MOSFET Package Design -- Chapter 6. Wafer Level Packaging TSV/Stack die for Integration of Analog and Power Solution -- Chapter 7. Thermal Management, Design, Analysis for WLCSP -- Chapter 8. Electrical and Multi-Physics Simulations for Analog and Power WLCSP -- Chapter 9. WLCSP Typical Assembly Process -- Chapter 10. WLCSP Typical Reliability and Test.
Contained By:	Springer eBooks
Subject:	Chip scale packaging. -
Online resource:	http://dx.doi.org/10.1007/978-1-4939-1556-9
ISBN:	9781493915569 (electronic bk.)

Wafer-level chip-scale packaging = analog and power semiconductor applications /
Qu, Shichun.

Wafer-level chip-scale packaginganalog and power semiconductor applications /[electronic resource] :by Shichun Qu, Yong Liu. - New York, NY :Springer New York :2015. - xvii, 322 p. :ill., digital ;24 cm.

Chapter 1. Demand and Challenges for Wafer Level Analog and Power Packaging -- Chapter 2. Fan-In Analog Wafer Level Chip Scale Package -- Chapter 3. Fan-Out Analog Wafer Level Chip Scale Package -- Chapter 4. Wafer Level Analog Chip Scale Package Stackable Design -- Chapter 5. Wafer Level Discrete Power MOSFET Package Design -- Chapter 6. Wafer Level Packaging TSV/Stack die for Integration of Analog and Power Solution -- Chapter 7. Thermal Management, Design, Analysis for WLCSP -- Chapter 8. Electrical and Multi-Physics Simulations for Analog and Power WLCSP -- Chapter 9. WLCSP Typical Assembly Process -- Chapter 10. WLCSP Typical Reliability and Test.

This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology Introduces the development of the analog and power SIP/3D/TSV/stack die packaging technology Presents the wafer-level analog IC packaging design through fan-in and fan-out with RDLs

ISBN: 9781493915569 (electronic bk.)

Standard No.: 10.1007/978-1-4939-1556-9doiSubjects--Topical Terms:

2132927
Chip scale packaging.

LC Class. No.: TK7870.17

Dewey Class. No.: 621

Wafer-level chip-scale packaging = analog and power semiconductor applications /
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245 1 0 $a Wafer-level chip-scale packaging $h [electronic resource] : $b analog and power semiconductor applications / $c by Shichun Qu, Yong Liu.
260 $a New York, NY : $b Springer New York : $b Imprint: Springer, $c 2015.
300 $a xvii, 322 p. : $b ill., digital ; $c 24 cm.
505 0 $a Chapter 1. Demand and Challenges for Wafer Level Analog and Power Packaging -- Chapter 2. Fan-In Analog Wafer Level Chip Scale Package -- Chapter 3. Fan-Out Analog Wafer Level Chip Scale Package -- Chapter 4. Wafer Level Analog Chip Scale Package Stackable Design -- Chapter 5. Wafer Level Discrete Power MOSFET Package Design -- Chapter 6. Wafer Level Packaging TSV/Stack die for Integration of Analog and Power Solution -- Chapter 7. Thermal Management, Design, Analysis for WLCSP -- Chapter 8. Electrical and Multi-Physics Simulations for Analog and Power WLCSP -- Chapter 9. WLCSP Typical Assembly Process -- Chapter 10. WLCSP Typical Reliability and Test.
520 $a This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology Introduces the development of the analog and power SIP/3D/TSV/stack die packaging technology Presents the wafer-level analog IC packaging design through fan-in and fan-out with RDLs
650 0 $a Chip scale packaging. $3 2132927
650 1 4 $a Engineering. $3 586835
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 893838
650 2 4 $a Circuits and Systems. $3 896527
650 2 4 $a Engineering Thermodynamics, Heat and Mass Transfer. $3 1002079
700 1 $a Liu, Yong. $3 1044700
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