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Functional verification of dynamical...

Gong, Lingkan.

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Functional verification of dynamically reconfigurable FPGA-based systems

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Functional verification of dynamically reconfigurable FPGA-based systems/ by Lingkan Gong, Oliver Diessel.
作者:	Gong, Lingkan.
其他作者:	Diessel, Oliver.
出版者:	Cham :Springer International Publishing : : 2015.,
面頁冊數:	xxi, 216 p. :ill., digital ;24 cm.
內容註:	Introduction -- Verification Challenges -- Modeling Reconfiguration -- Getting Started with Verification -- Case Studies -- References Designs -- Conclusions.-- Appendix A: Bugs Detected in Case Studies -- Appendix B: Inside the ReSim Library -- References.
Contained By:	Springer eBooks
標題:	Field programmable gate arrays. -
電子資源:	http://dx.doi.org/10.1007/978-3-319-06838-1
ISBN:	9783319068381 (electronic bk.)

Functional verification of dynamically reconfigurable FPGA-based systems
Gong, Lingkan.

Functional verification of dynamically reconfigurable FPGA-based systems[electronic resource] /by Lingkan Gong, Oliver Diessel. - Cham :Springer International Publishing :2015. - xxi, 216 p. :ill., digital ;24 cm.

Introduction -- Verification Challenges -- Modeling Reconfiguration -- Getting Started with Verification -- Case Studies -- References Designs -- Conclusions.-- Appendix A: Bugs Detected in Case Studies -- Appendix B: Inside the ReSim Library -- References.

This book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric. Two implementations of the simulation-only layer are included: Extended ReChannel is a SystemC library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification. Provides researchers with an in-depth understanding of the challenges in verifying dynamically reconfigurable systems and the state-of-the-art methods used to overcome them; Guides engineers with systematic approaches and tools to achieve verification closure in their dynamically reconfigurable projects; Includes a comprehensive set of case studies, with an analysis of real bugs detected in the designs described; Uses tools and techniques compatible with mainstream products (e.g. Xilinx/Altera tools, ModelSim simulator, Verilog/VHDL design language, etc)

ISBN: 9783319068381 (electronic bk.)

Standard No.: 10.1007/978-3-319-06838-1doiSubjects--Topical Terms:

666370
Field programmable gate arrays.

LC Class. No.: TK7895.G36

Dewey Class. No.: 621.395

Functional verification of dynamically reconfigurable FPGA-based systems
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