A pipelined multi-core MIPS machine ...
Kovalev, Mikhail.

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  • A pipelined multi-core MIPS machine = hardware implementation and correctness proof /
  • Record Type: Electronic resources : Monograph/item
    Title/Author: A pipelined multi-core MIPS machine/ by Mikhail Kovalev, Silvia M. Muller, Wolfgang J. Paul.
    Reminder of title: hardware implementation and correctness proof /
    other author: Kovalev, Mikhail.
    Published: Cham :Springer International Publishing : : 2014.,
    Description: xii, 352 p. :ill., digital ;24 cm.
    Contained By: Springer eBooks
    Subject: MIPS (Computer architecture) -
    Online resource: http://dx.doi.org/10.1007/978-3-319-13906-7
    ISBN: 9783319139067 (electronic bk.)
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W9265052 電子資源 11.線上閱覽_V 電子書 EB QA76.9.A73 P57 2014 一般使用(Normal) On shelf 0
  • 1 records • Pages 1 •
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