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Scheduling and partitioning VLSI cir...

Wang, Ling.

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Scheduling and partitioning VLSI circuit operating at multiple supply voltages.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Scheduling and partitioning VLSI circuit operating at multiple supply voltages./
Author:	Wang, Ling.
Description:	92 p.
Notes:	Source: Dissertation Abstracts International, Volume: 64-12, Section: B, page: 6257.
Contained By:	Dissertation Abstracts International64-12B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3115899

Scheduling and partitioning VLSI circuit operating at multiple supply voltages.
Wang, Ling.

Scheduling and partitioning VLSI circuit operating at multiple supply voltages. - 92 p.

Source: Dissertation Abstracts International, Volume: 64-12, Section: B, page: 6257.

Thesis (Ph.D.)--University of Nevada, Las Vegas, 2003.

With today's increasingly large and complex digital integrated circuit (IC) and system-on-chip designs, power dissipation has emerged as a primary design consideration. Reduction of power consumption in VLSI designs can be achieved at various levels of the design hierarchy, ranging from processing technology, circuit, logic, architectural and algorithmic (behavioral) levels, up to system level. It has also been long recognized that the most dramatic power saving is achievable at the algorithm and architecture levels, where computations are normally described using data/control flow graph. Thus, in this thesis, a multiple supply voltage IC is synthesized at the behavior level.Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Scheduling and partitioning VLSI circuit operating at multiple supply voltages.
LDR:03560nmm 2200313 4500 001 1864511
005 20041216132052.5
008 130614s2003 eng d
035 $a (UnM)AAI3115899
035 $a AAI3115899
040 $a UnM $c UnM
100 1 $a Wang, Ling. $3 519909
245 1 0 $a Scheduling and partitioning VLSI circuit operating at multiple supply voltages.
300 $a 92 p.
500 $a Source: Dissertation Abstracts International, Volume: 64-12, Section: B, page: 6257.
500 $a Chair: Henry Selvaraj.
502 $a Thesis (Ph.D.)--University of Nevada, Las Vegas, 2003.
520 $a With today's increasingly large and complex digital integrated circuit (IC) and system-on-chip designs, power dissipation has emerged as a primary design consideration. Reduction of power consumption in VLSI designs can be achieved at various levels of the design hierarchy, ranging from processing technology, circuit, logic, architectural and algorithmic (behavioral) levels, up to system level. It has also been long recognized that the most dramatic power saving is achievable at the algorithm and architecture levels, where computations are normally described using data/control flow graph. Thus, in this thesis, a multiple supply voltage IC is synthesized at the behavior level.
520 $a There are, however, a number of practical problems that must be overcome before use of multiple supply voltage becomes prevalent. In particular, lower power is achieved along with an expensive routing cost. Therefore, unlike the existing methods where only scheduling is considered, our synthesis scheme considers both scheduling and partitioning to reduce power consumption due to the functional units as well as the routing cost.
520 $a The concerned problem is subsequently referred as the multiple voltage scheduling and partitioning problem (MVSP). The MVSP problem is proved to be NP-complete and three behavioral level synthesis algorithms are proposed to minimize power consumption with resources operating at multiple voltages. One is the polynomial time algorithm. The others are heuristic algorithms, which are tabu search algorithm (TS), and simulated annealing algorithm (SA).
520 $a In the polynomial time algorithm, synthesis is based on the following three-step process. First, one particular supply voltage (selected from a finite and known number of supply voltage levels) is to be determined for each operation in a data flow graph. Then various operations are scheduled so that the power consumption under given time and/or resource constraints can be minimized. Finally, operations are partitioned into different regions running in different supply voltages to minimize the interconnection costs.
520 $a In TS and SA algorithms, synthesis schemes are performed to minimize the power consumed by resources and interconnections. In particular, we have configured our solutions with a three-tuple vector to account for both the resource assignment and the partition of operation nodes. Special move operation is designed that allows the scheduling and the partitioning to be performed simultaneously.
520 $a Experiments with a number of digital signal processing benchmarks show that the proposed algorithms achieve the power reduction at different percentage.
590 $a School code: 0506.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 0 $a University of Nevada, Las Vegas. $3 1017627
773 0 $t Dissertation Abstracts International $g 64-12B.
790 1 0 $a Selvaraj, Henry, $e advisor
790 $a 0506
791 $a Ph.D.
792 $a 2003
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3115899