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Scaling limits and opportunities of ...

Chen, Qiang.

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Scaling limits and opportunities of double-gate MOSFETs.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Scaling limits and opportunities of double-gate MOSFETs./
Author:	Chen, Qiang.
Description:	238 p.
Notes:	Source: Dissertation Abstracts International, Volume: 64-03, Section: B, page: 1392.
Contained By:	Dissertation Abstracts International64-03B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3084946
ISBN:	0496327539

Scaling limits and opportunities of double-gate MOSFETs.
Chen, Qiang.

Scaling limits and opportunities of double-gate MOSFETs. - 238 p.

Source: Dissertation Abstracts International, Volume: 64-03, Section: B, page: 1392.

Thesis (Ph.D.)--Georgia Institute of Technology, 2003.

Scaling limits and opportunities of undoped double-gate MOSFETs are investigated by developing compact, physics-based, analytical models of subthreshold swing and threshold voltage under various modes of operation (i.e., symmetric, asymmetric, and ground-plane). These models are based on two-dimensional analyses of electrostatics in the channel region by solving two-dimensional Poisson equations. Newly developed models are applied to comprehensively investigate threshold voltage variations caused by process tolerances of device parameters including the channel length, channel thickness, and gate oxide thickness. Applicability of ground-plane MOSFETs with independent gate biases toward variable threshold voltage technique is explored. A scale length is derived that readily identifies design requirements for short-channel-effect resistant double-gate MOSFETs. Impact of high-permittivity gate dielectrics on double-gate MOSFET scalability is assessed in a concerted manner, which is enabled by a compact gate direct tunneling current model and a newly developed threshold voltage model incorporating fringe-induced-barrier-lowering effects. Scaling limits of double-gate MOSFETs are projected based on various criteria, including turn-off characteristic requirements and parameter variation requirements. Model predictions indicate that the ability to tightly control process tolerances will set the ultimate limit on scaling of undoped DG MOSFETs as a building element, rather than as an individual device, for gigascale integration.

ISBN: 0496327539Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Scaling limits and opportunities of double-gate MOSFETs.
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100 1 $a Chen, Qiang. $3 1267620
245 1 0 $a Scaling limits and opportunities of double-gate MOSFETs.
300 $a 238 p.
500 $a Source: Dissertation Abstracts International, Volume: 64-03, Section: B, page: 1392.
500 $a Director: James D. Meindl.
502 $a Thesis (Ph.D.)--Georgia Institute of Technology, 2003.
520 $a Scaling limits and opportunities of undoped double-gate MOSFETs are investigated by developing compact, physics-based, analytical models of subthreshold swing and threshold voltage under various modes of operation (i.e., symmetric, asymmetric, and ground-plane). These models are based on two-dimensional analyses of electrostatics in the channel region by solving two-dimensional Poisson equations. Newly developed models are applied to comprehensively investigate threshold voltage variations caused by process tolerances of device parameters including the channel length, channel thickness, and gate oxide thickness. Applicability of ground-plane MOSFETs with independent gate biases toward variable threshold voltage technique is explored. A scale length is derived that readily identifies design requirements for short-channel-effect resistant double-gate MOSFETs. Impact of high-permittivity gate dielectrics on double-gate MOSFET scalability is assessed in a concerted manner, which is enabled by a compact gate direct tunneling current model and a newly developed threshold voltage model incorporating fringe-induced-barrier-lowering effects. Scaling limits of double-gate MOSFETs are projected based on various criteria, including turn-off characteristic requirements and parameter variation requirements. Model predictions indicate that the ability to tightly control process tolerances will set the ultimate limit on scaling of undoped DG MOSFETs as a building element, rather than as an individual device, for gigascale integration.
590 $a School code: 0078.
650 4 $a Engineering, Electronics and Electrical. $3 626636
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710 2 0 $a Georgia Institute of Technology. $3 696730
773 0 $t Dissertation Abstracts International $g 64-03B.
790 1 0 $a Meindl, James D., $e advisor
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791 $a Ph.D.
792 $a 2003
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3084946