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Piecewise linear delay modeling of d...

Chang, Jian.

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Piecewise linear delay modeling of digital VLSI circuits.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Piecewise linear delay modeling of digital VLSI circuits./
Author:	Chang, Jian.
Description:	154 p.
Notes:	Source: Dissertation Abstracts International, Volume: 67-03, Section: B, page: 1593.
Contained By:	Dissertation Abstracts International67-03B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3211653
ISBN:	9780542603969

Piecewise linear delay modeling of digital VLSI circuits.
Chang, Jian.

Piecewise linear delay modeling of digital VLSI circuits. - 154 p.

Source: Dissertation Abstracts International, Volume: 67-03, Section: B, page: 1593.

Thesis (Ph.D.)--Oklahoma State University, 2006.

Scope and method of study. One of the most important performance measures of digital logic circuits is the delays of switching signals propagating through the logic gates of the circuit. Circuit simulators such as SPICE can find the delay by solving for the current and voltage waveforms as functions of time. Although SPICE can handle the complex, nonlinear behavior of the transistors, it takes a significant amount of computations. Usually no more than a few thousand transistors may be simulated in a reasonable amount of computation time. Simulator such as IRSIM uses the switch model to find the delay, which greatly improves the simulation speed and can process hundreds of thousands of transistors in a reasonable amount of time. But IRSIM predicts delays much less accurate than SPICE because of its delay model inaccuracies. In this paper, a piecewise linear delay model which can evaluate the propagation delay of a CMOS VLSI circuitry with a wide range of input slope is presented. The model also takes into account the influences of short circuit current and dynamic channel charges. By using simple piecewise linear current model and piecewise linear channel charge storage model, it is possible to simulate the modern digital logic circuits in a reasonable amount of time. This model is applicable not only to propagation delay calculation of simple gates but also to that of any general circuit topology.

ISBN: 9780542603969Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Piecewise linear delay modeling of digital VLSI circuits.
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035 $a (UMI)AAI3211653
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100 1 $a Chang, Jian. $3 1910576
245 1 0 $a Piecewise linear delay modeling of digital VLSI circuits.
300 $a 154 p.
500 $a Source: Dissertation Abstracts International, Volume: 67-03, Section: B, page: 1593.
500 $a Adviser: Louis G. Johnson.
502 $a Thesis (Ph.D.)--Oklahoma State University, 2006.
520 $a Scope and method of study. One of the most important performance measures of digital logic circuits is the delays of switching signals propagating through the logic gates of the circuit. Circuit simulators such as SPICE can find the delay by solving for the current and voltage waveforms as functions of time. Although SPICE can handle the complex, nonlinear behavior of the transistors, it takes a significant amount of computations. Usually no more than a few thousand transistors may be simulated in a reasonable amount of computation time. Simulator such as IRSIM uses the switch model to find the delay, which greatly improves the simulation speed and can process hundreds of thousands of transistors in a reasonable amount of time. But IRSIM predicts delays much less accurate than SPICE because of its delay model inaccuracies. In this paper, a piecewise linear delay model which can evaluate the propagation delay of a CMOS VLSI circuitry with a wide range of input slope is presented. The model also takes into account the influences of short circuit current and dynamic channel charges. By using simple piecewise linear current model and piecewise linear channel charge storage model, it is possible to simulate the modern digital logic circuits in a reasonable amount of time. This model is applicable not only to propagation delay calculation of simple gates but also to that of any general circuit topology.
520 $a Findings and conclusions. Excellent agreements with SPICE simulation have been observed in a CMOS inverter, a two-input NAND gate, and an OAI gate cases. The piecewise linear model is capable of predicting the output waveforms and the propagation delay over a variety of input and output conditions. The piecewise linear model can handle large complicated circuits by introducing smaller resistance connected regions. The model is also scalable from one technology to another by choosing different set of technology related model parameters. In general, it is possible to implement a fast circuit simulator based on the piecewise linear model or include the piecewise linear model into an existing circuit simulator such as IRSIM because of its accuracy and speed advantages.
590 $a School code: 0664.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 0 $a Oklahoma State University. $3 626630
773 0 $t Dissertation Abstracts International $g 67-03B.
790 1 0 $a Johnson, Louis G., $e advisor
790 $a 0664
791 $a Ph.D.
792 $a 2006
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3211653