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High-resolution time measurement and...

Levine, Peter.

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High-resolution time measurement and calibration for on-chip test systems.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	High-resolution time measurement and calibration for on-chip test systems./
作者:	Levine, Peter.
面頁冊數:	61 p.
附註:	Source: Masters Abstracts International, Volume: 44-02, page: 0996.
Contained By:	Masters Abstracts International44-02.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=MR06567
ISBN:	9780494065679

High-resolution time measurement and calibration for on-chip test systems.
Levine, Peter.

High-resolution time measurement and calibration for on-chip test systems. - 61 p.

Source: Masters Abstracts International, Volume: 44-02, page: 0996.

Thesis (M.Eng.)--McGill University (Canada), 2004.

Verification of timing performance in integrated circuits (ICs) is becoming more difficult as clock frequencies and levels of integration increase. As a result, on-chip timing measurement has become a very attractive solution because it helps to overcome the bandwidth and test access limitations inherent in traditional off-chip test systems.

ISBN: 9780494065679Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

High-resolution time measurement and calibration for on-chip test systems.
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502 $a Thesis (M.Eng.)--McGill University (Canada), 2004.
520 $a Verification of timing performance in integrated circuits (ICs) is becoming more difficult as clock frequencies and levels of integration increase. As a result, on-chip timing measurement has become a very attractive solution because it helps to overcome the bandwidth and test access limitations inherent in traditional off-chip test systems.
520 $a Flash time-to-digital converters (TDCs) are well-suited for use in on-chip timing measurement systems because they can be operated at high speeds, offer low test time, and are relatively easy to integrate. However, clock jitter in modern ICs is often on the same order of magnitude as the temporal resolution of the TDC itself. Therefore, techniques are required to increase the resolution of these devices, while ensuring timing accuracy.
520 $a This thesis presents a high-resolution flash TDC that exploits the random offsets on flip-flops or arbiters to perform time quantization. It also describes a novel technique based on additive temporal noise to accurately calibrate the measurement device. Simulation and experimental results reveal that this method can calibrate the high-resolution flash TDC down to 5 ps within reasonable error limits. In addition, accurate timing measurement of jitter below 14 ps has been experimentally validated using a custom flash TDC fabricated in a 0.18-mum CMOS process.
520 $a A review of the most common circuit techniques for timing measurement is also included in this thesis. Furthermore, a calibration system implementation that can be used to reduce the temporal resolution requirements of phase-generation circuitry is proposed.
590 $a School code: 0781.
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