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Design of a 14-bit continuous-time d...

Li, Zhimin.

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Design of a 14-bit continuous-time delta-sigma A/D modulator with 2.5MHz signal bandwidth.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Design of a 14-bit continuous-time delta-sigma A/D modulator with 2.5MHz signal bandwidth./
Author:	Li, Zhimin.
Description:	139 p.
Notes:	Source: Dissertation Abstracts International, Volume: 67-02, Section: B, page: 1059.
Contained By:	Dissertation Abstracts International67-02B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3207151
ISBN:	9780542541612

Design of a 14-bit continuous-time delta-sigma A/D modulator with 2.5MHz signal bandwidth.
Li, Zhimin.

Design of a 14-bit continuous-time delta-sigma A/D modulator with 2.5MHz signal bandwidth. - 139 p.

Source: Dissertation Abstracts International, Volume: 67-02, Section: B, page: 1059.

Thesis (Ph.D.)--Oregon State University, 2006.

In recent years, there has been growing interest in both industry and academia to use continuous-time (CT) Delta-Sigma A/D converters for wideband wireless and wireline communication applications.

ISBN: 9780542541612Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Design of a 14-bit continuous-time delta-sigma A/D modulator with 2.5MHz signal bandwidth.
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035 $a (UnM)AAI3207151
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040 $a UnM $c UnM
100 1 $a Li, Zhimin. $3 1919534
245 1 0 $a Design of a 14-bit continuous-time delta-sigma A/D modulator with 2.5MHz signal bandwidth.
300 $a 139 p.
500 $a Source: Dissertation Abstracts International, Volume: 67-02, Section: B, page: 1059.
500 $a Adviser: Terri S. Fiez.
502 $a Thesis (Ph.D.)--Oregon State University, 2006.
520 $a In recent years, there has been growing interest in both industry and academia to use continuous-time (CT) Delta-Sigma A/D converters for wideband wireless and wireline communication applications.
520 $a So far no reported CT Delta-Sigma A/D modulator achieves 14-bit or higher dynamic range (DR) with more than 2MHz signal bandwidth (equivalently 4MS/s). This dissertation presents the realization of a continuous-time (CT) Delta-Sigma A/D modulator providing 80.5dB DR and 85dB DR with 5MS/s output data rate in a 2.5V 0.25mum CMOS process. The modulator has a single-stage dual-loop architecture allowing large quantizer delay. A 17-level quantizer is used to increase resolution and non-return-to-zero DACs are adopted to reduce clock jitter sensitivity. Capacitor tuning is utilized to overcome time-constant variation. On-chip self-calibration is implemented to suppress DAC nonlinearity. Combining techniques to address various design challenges, the modulator consumes 50mW with 60MHz sampling rate.
590 $a School code: 0172.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 0 $a Oregon State University. $3 625720
773 0 $t Dissertation Abstracts International $g 67-02B.
790 1 0 $a Fiez, Terri S., $e advisor
790 $a 0172
791 $a Ph.D.
792 $a 2006
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3207151