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Gate-level techniques for low power ...

Gao, Feng.

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Gate-level techniques for low power and reliable circuit design.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Gate-level techniques for low power and reliable circuit design./
作者:	Gao, Feng.
面頁冊數:	140 p.
附註:	Source: Dissertation Abstracts International, Volume: 66-10, Section: B, page: 5495.
Contained By:	Dissertation Abstracts International66-10B.
標題:	Computer Science. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3192639
ISBN:	9780542364839

Gate-level techniques for low power and reliable circuit design.
Gao, Feng.

Gate-level techniques for low power and reliable circuit design. - 140 p.

Source: Dissertation Abstracts International, Volume: 66-10, Section: B, page: 5495.

Thesis (Ph.D.)--University of Michigan, 2005.

The continuous scaling down of transistor feature size poses several challenges to integrated circuit (IC) design. First, both dynamic and leakage power consumption keep increasing. In addition, transistors are becoming more susceptible to soft errors caused by cosmic radiation or signal noise. The overall goal of this research is to develop effective gate-level techniques to reduce the power consumption of digital circuits and to increase their reliability.

ISBN: 9780542364839Subjects--Topical Terms:

626642
Computer Science.

Gate-level techniques for low power and reliable circuit design.
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502 $a Thesis (Ph.D.)--University of Michigan, 2005.
520 $a The continuous scaling down of transistor feature size poses several challenges to integrated circuit (IC) design. First, both dynamic and leakage power consumption keep increasing. In addition, transistors are becoming more susceptible to soft errors caused by cosmic radiation or signal noise. The overall goal of this research is to develop effective gate-level techniques to reduce the power consumption of digital circuits and to increase their reliability.
520 $a This thesis develops optimal and heuristic algorithms to solve several power minimization and circuit reliability problems. We first show how to find an input vector that results in minimum leakage current while a circuit is in the inactive or idle mode. An integer linear programming (ILP) model of the problem is developed, along with new techniques to reduce the number of variables in the model. A near-optimal mixed-integer linear programming (MLP) model is then derived from the ILP model. We demonstrate that applying the input vector with minimum leakage can usually reduce the leakage power consumption by 25%. The effectiveness of the MLP model (with less than 5% leakage power overhead) is shown by comparison with existing approaches. We then address simultaneous gate sizing and Vt assignment for power minimization. A novel way to linearize the circuit delay function is proposed, which enables the construction of exact MLP models for power minimization by gate sizing and Vt assignment. Application of such models to leakage and total power minimization problems shows the power saving advantages of exact MLP models over heuristic-based approaches. We also propose a method to decompose a finite-state machine into submachines which can be switched off selectively for dynamic power reduction. Significant power savings are demonstrated by simulation experiments. In addition, we develop a systematic way of creating a circuit to monitor soft errors in a finite-state machines. The monitoring circuit is shown to have low area overhead, high fault coverage, and short fault detection delay.
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