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Unified synthesis techniques for hig...

Chen, Gang.

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Unified synthesis techniques for high performance FPGA designs.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Unified synthesis techniques for high performance FPGA designs./
作者:	Chen, Gang.
面頁冊數:	134 p.
附註:	Source: Dissertation Abstracts International, Volume: 66-05, Section: B, page: 2671.
Contained By:	Dissertation Abstracts International66-05B.
標題:	Computer Science. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3175218
ISBN:	054213473X

Unified synthesis techniques for high performance FPGA designs.
Chen, Gang.

Unified synthesis techniques for high performance FPGA designs. - 134 p.

Source: Dissertation Abstracts International, Volume: 66-05, Section: B, page: 2671.

Thesis (Ph.D.)--University of California, Los Angeles, 2005.

As the device geometry keeps shrinking in today's deep sub-micron technologies, interconnect delay dominates the critical path. In the current FPGA design flow, there are two major drawbacks: the separation of technology-independent optimization and technology mapping in the traditional logic synthesis flow, and the separation of logic synthesis and physical implementation in the traditional implementation flow. Such drawbacks result in sub-optimal performance and a long timing closure cycle. In this thesis we propose the utilization of unified synthesis techniques in the context of FPGAs to address these issues and improve the overall design performance. In Chapter 3 we bridge the gap between technology-independent optimization and technology mapping by combining logic decomposition and mapping. In Chapter 4, we introduce a novel algorithm named SCPlace [17] to perform simultaneous clustering during placement. In Chapter 5 we introduce an algorithm named SPD to perform logic duplication during placement. In Chapter 6 we build the first complete academic CAD flow, which can be easily plugged in to a state-of-the-art commercial tool, Altera's Quartus 4.0 software. Our unified synthesis and placement tool, SPCD, combines both the clustering and duplication techniques. Our experimental results show up to over 30% improvement in performance compared with the current state-of-the-art academic flow.

ISBN: 054213473XSubjects--Topical Terms:

626642
Computer Science.

Unified synthesis techniques for high performance FPGA designs.
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520 $a As the device geometry keeps shrinking in today's deep sub-micron technologies, interconnect delay dominates the critical path. In the current FPGA design flow, there are two major drawbacks: the separation of technology-independent optimization and technology mapping in the traditional logic synthesis flow, and the separation of logic synthesis and physical implementation in the traditional implementation flow. Such drawbacks result in sub-optimal performance and a long timing closure cycle. In this thesis we propose the utilization of unified synthesis techniques in the context of FPGAs to address these issues and improve the overall design performance. In Chapter 3 we bridge the gap between technology-independent optimization and technology mapping by combining logic decomposition and mapping. In Chapter 4, we introduce a novel algorithm named SCPlace [17] to perform simultaneous clustering during placement. In Chapter 5 we introduce an algorithm named SPD to perform logic duplication during placement. In Chapter 6 we build the first complete academic CAD flow, which can be easily plugged in to a state-of-the-art commercial tool, Altera's Quartus 4.0 software. Our unified synthesis and placement tool, SPCD, combines both the clustering and duplication techniques. Our experimental results show up to over 30% improvement in performance compared with the current state-of-the-art academic flow.
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