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An RC-based voltage-variable delay e...

Zhang, Yang.

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An RC-based voltage-variable delay element.

Record Type:	Electronic resources : Monograph/item
Title/Author:	An RC-based voltage-variable delay element./
Author:	Zhang, Yang.
Description:	87 p.
Notes:	Source: Masters Abstracts International, Volume: 43-06, page: 2371.
Contained By:	Masters Abstracts International43-06.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=MR01082
ISBN:	0494010827

An RC-based voltage-variable delay element.
Zhang, Yang.

An RC-based voltage-variable delay element. - 87 p.

Source: Masters Abstracts International, Volume: 43-06, page: 2371.

Thesis (M.Sc.(Eng))--Queen's University at Kingston (Canada), 2005.

Variable delay elements are one of the basic units in digital logic circuits to produce an output waveform similar to its input waveform, only delayed by a controllable amount of time. They are often used to manipulate the rising or falling edges of the clock or any other signal in digital systems, for example phase-locked-loops (PLLs) and delay-locked-loops (DLLs), which are crucial components in clock management circuits. In this project, we propose a new delay element in resistor-capacitor (RC) architecture and develop an analytical equation for the relationship of the output delay time and the control voltage. The proposed circuit exhibits improved delay characteristics over previously reported inverter-chains delay elements and could apply to any duty-cycle digital signals besides square clock waveforms. The chip was fabricated under TSMC 0.18u CMOS technology with the collaboration of Canadian Microelectronics Corporation (CMC). The maximum operation data rate could be up to 2Gbps.

ISBN: 0494010827Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

An RC-based voltage-variable delay element.
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035 $a (UnM)AAIMR01082
035 $a AAIMR01082
040 $a UnM $c UnM
100 1 $a Zhang, Yang. $3 1025673
245 1 3 $a An RC-based voltage-variable delay element.
300 $a 87 p.
500 $a Source: Masters Abstracts International, Volume: 43-06, page: 2371.
500 $a Adviser: Carlos E. Saavedra.
502 $a Thesis (M.Sc.(Eng))--Queen's University at Kingston (Canada), 2005.
520 $a Variable delay elements are one of the basic units in digital logic circuits to produce an output waveform similar to its input waveform, only delayed by a controllable amount of time. They are often used to manipulate the rising or falling edges of the clock or any other signal in digital systems, for example phase-locked-loops (PLLs) and delay-locked-loops (DLLs), which are crucial components in clock management circuits. In this project, we propose a new delay element in resistor-capacitor (RC) architecture and develop an analytical equation for the relationship of the output delay time and the control voltage. The proposed circuit exhibits improved delay characteristics over previously reported inverter-chains delay elements and could apply to any duty-cycle digital signals besides square clock waveforms. The chip was fabricated under TSMC 0.18u CMOS technology with the collaboration of Canadian Microelectronics Corporation (CMC). The maximum operation data rate could be up to 2Gbps.
590 $a School code: 0283.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 0 $a Queen's University at Kingston (Canada). $3 1250078
773 0 $t Masters Abstracts International $g 43-06.
790 1 0 $a Saavedra, Carlos E., $e advisor
790 $a 0283
791 $a M.Sc.(Eng)
792 $a 2005
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=MR01082