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Multi-softcore architectures and alg...

Wang, Qingbo.

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Multi-softcore architectures and algorithms for a class of sparse computations.

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Multi-softcore architectures and algorithms for a class of sparse computations./
Author:	Wang, Qingbo.
Description:	131 p.
Notes:	Source: Dissertation Abstracts International, Volume: 71-09, Section: B, page: 5698.
Contained By:	Dissertation Abstracts International71-09B.
Subject:	Engineering, Computer. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3418198
ISBN:	9781124162515

Multi-softcore architectures and algorithms for a class of sparse computations.
Wang, Qingbo.

Multi-softcore architectures and algorithms for a class of sparse computations. - 131 p.

Source: Dissertation Abstracts International, Volume: 71-09, Section: B, page: 5698.

Thesis (Ph.D.)--University of Southern California, 2010.

Field-programmable gate array (FPGA) is a representative reconfigurable computing platform. It has been used in many applications to execute computationally intensive workloads. In this work, we study architectures and algorithms on FPGA for sparse computations. These computations have unique features: (1) the ratio of input and output operations to computation is high and (2) most memory accesses are random with little or no data locality, which leads to low memory bandwidth utilization.

ISBN: 9781124162515Subjects--Topical Terms:

1669061
Engineering, Computer.

Multi-softcore architectures and algorithms for a class of sparse computations.
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100 1 $a Wang, Qingbo. $3 1682550
245 1 0 $a Multi-softcore architectures and algorithms for a class of sparse computations.
300 $a 131 p.
500 $a Source: Dissertation Abstracts International, Volume: 71-09, Section: B, page: 5698.
500 $a Adviser: Viktor K. Prasanna.
502 $a Thesis (Ph.D.)--University of Southern California, 2010.
520 $a Field-programmable gate array (FPGA) is a representative reconfigurable computing platform. It has been used in many applications to execute computationally intensive workloads. In this work, we study architectures and algorithms on FPGA for sparse computations. These computations have unique features: (1) the ratio of input and output operations to computation is high and (2) most memory accesses are random with little or no data locality, which leads to low memory bandwidth utilization.
520 $a We propose Multiple Application Specific Softcore architecture to overcome the performance hurdles that are inherent to sparse computations. We identify the critical issues, demonstrate our solutions, and validate the proposed architecture using two case studies: large dictionary string matching and breadth-first search on a graph. Our architecture utilizes multiple application-specific processing units (softcores) to exploit the potential thread-level parallelism in these computations. To alleviate the impact of long latency from accessing external memory on system performance, a specialized memory architecture and a scheduling mechanism are devised to reduce the number of accesses to external memory and to hide the effects of the remaining accesses. By utilizing customized interconnects which are adaptive to communication demand, flexible and efficient inter-softcore data exchange and synchronization mechanism are well supported.
520 $a The two kernels in our study are among the most common sparse computation algorithms and are of practical significance on their own. String matching searches for all occurrences of a set of patterns (the dictionary) in a string of input data. It is the core function of search engines, intrusion detection systems (IDS), virus scanners, and spam and content filters. In our study on large dictionary string matching, our design achieved a throughput comparable to implementations on state-of-the-art multi-core computing systems. Breadth-first search is a fundamental building block for many graph algorithms, with applications in network analysis, image processing, and database query. Breadth-first search is a difficult kernel to parallelize on cache-based multi-core systems due to its fine-grained random data access and synchronization between threads. We demonstrate that, by using a message passing multi-core architecture with a distributed barrier design, high throughput performance can be obtained using a modest amount of logic resources on FPGA.
590 $a School code: 0208.
650 4 $a Engineering, Computer. $3 1669061
650 4 $a Engineering, Electronics and Electrical. $3 626636
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690 $a 0544
710 2 $a University of Southern California. $b Electrical Engineering. $3 1020963
773 0 $t Dissertation Abstracts International $g 71-09B.
790 1 0 $a Prasanna, Viktor K., $e advisor
790 1 0 $a Ung, Monte $e committee member
790 1 0 $a Nakano, Aiichiro $e committee member
790 $a 0208
791 $a Ph.D.
792 $a 2010
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3418198