Radecka, Katarzyna.
Overview
| Works: | 2 works in 0 publications in 0 languages | |
|---|---|---|
Titles
Verification by error modeling = using testing techniques in hardware verification /
by:
Zilic, Zeljko.; NetLibrary, Inc.; Radecka, Katarzyna.
(Language materials, printed)
Verification by error modeling : = using testing techniques in hardware verification
by:
Zilic, Zeljko.; SpringerLink (Online service); Radecka, Katarzyna.
(Language materials, printed)