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Three-dimensional integrated circuit...

Friedman, Eby G.

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Three-dimensional integrated circuit design

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Three-dimensional integrated circuit design/ Vasilis F. Pavlidis, Eby G. Friedman.
Author:	Pavlidis, Vasilis F.,
other author:	Friedman, Eby G.
Published:	Amsterdam ;Morgan Kaufmann, : c2009.,
Description:	xv, 309 p. :ill. ;25 cm.
Series:	The Morgan Kaufmann series in systems on silicon
[NT 15003449]:	Chapter 1. Introduction -- Chapter 2. Manufacturing of 3-D Packaged Systems -- Chapter 3. 3-D Integrated Circuit Fabrication Technologies -- Chapter 4. Interconnect Prediction Models -- Chapter 5. Physical Design Techniques for 3-D ICs -- Chapter 6. Thermal Management Techniques -- Chapter 7. Timing Optimization for Two-Terminal Interconnects -- Chapter 8. Timing Optimization for Multi-Terminal Interconnects -- Appendix A: Enumeration of Gate Pairs in a 3-D IC --Appendix B: Formal Proof of Optimum Single Via Placement -- Appendix C: Proof of the Two-Terminal Via Placement Heuristic -- Appendix D: Proof of Condition for Via Placement of Multi-Terminal Nets -- References.
Subject:	Integrated circuits - Design and construction. -
Online resource:	http://www.engineeringvillage.com/controller/servlet/OpenURL?genre=book&isbn=9780123743435An electronic book accessible through the World Wide Web; click for information
Online resource:	http://www.sciencedirect.com/science/book/9780123743435An electronic book accessible through the World Wide Web; click for information
ISBN:	0123743435

Three-dimensional integrated circuit design
Pavlidis, Vasilis F.,1976-

Three-dimensional integrated circuit design[electronic resource] /Vasilis F. Pavlidis, Eby G. Friedman. - Amsterdam ;Morgan Kaufmann,c2009. - xv, 309 p. :ill. ;25 cm. - The Morgan Kaufmann series in systems on silicon.

Includes bibliographical references (p. 289-303) and index.

Chapter 1. Introduction -- Chapter 2. Manufacturing of 3-D Packaged Systems -- Chapter 3. 3-D Integrated Circuit Fabrication Technologies -- Chapter 4. Interconnect Prediction Models -- Chapter 5. Physical Design Techniques for 3-D ICs -- Chapter 6. Thermal Management Techniques -- Chapter 7. Timing Optimization for Two-Terminal Interconnects -- Chapter 8. Timing Optimization for Multi-Terminal Interconnects -- Appendix A: Enumeration of Gate Pairs in a 3-D IC --Appendix B: Formal Proof of Optimum Single Via Placement -- Appendix C: Proof of the Two-Terminal Via Placement Heuristic -- Appendix D: Proof of Condition for Via Placement of Multi-Terminal Nets -- References.

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance.

Electronic reproduction.
Amsterdam :
Elsevier Science & Technology,
2009.

Mode of access: World Wide Web.

ISBN: 0123743435

Source: 152801:152956Elsevier Science & Technologyhttp://www.sciencedirect.comSubjects--Topical Terms:

658490
Integrated circuits
--Design and construction.Index Terms--Genre/Form:

542853
Electronic books.

LC Class. No.: TK7874 / .P39 2009

Dewey Class. No.: 621.3815

Three-dimensional integrated circuit design
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100 1 $a Pavlidis, Vasilis F., $d 1976- $3 1068961
245 1 0 $a Three-dimensional integrated circuit design $h [electronic resource] / $c Vasilis F. Pavlidis, Eby G. Friedman.
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300 $a xv, 309 p. : $b ill. ; $c 25 cm.
440 4 $a The Morgan Kaufmann series in systems on silicon
504 $a Includes bibliographical references (p. 289-303) and index.
505 0 $a Chapter 1. Introduction -- Chapter 2. Manufacturing of 3-D Packaged Systems -- Chapter 3. 3-D Integrated Circuit Fabrication Technologies -- Chapter 4. Interconnect Prediction Models -- Chapter 5. Physical Design Techniques for 3-D ICs -- Chapter 6. Thermal Management Techniques -- Chapter 7. Timing Optimization for Two-Terminal Interconnects -- Chapter 8. Timing Optimization for Multi-Terminal Interconnects -- Appendix A: Enumeration of Gate Pairs in a 3-D IC --Appendix B: Formal Proof of Optimum Single Via Placement -- Appendix C: Proof of the Two-Terminal Via Placement Heuristic -- Appendix D: Proof of Condition for Via Placement of Multi-Terminal Nets -- References.
520 $a With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance.
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650 0 $a Integrated circuits $x Design and construction. $3 658490
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