Language:
English
繁體中文
Help
回圖書館首頁
手機版館藏查詢
Login
Back
Switch To:
Labeled
|
MARC Mode
|
ISBD
Linked to FindBook
Google Book
Amazon
博客來
Verification by error modeling = using testing techniques in hardware verification /
Record Type:
Electronic resources : Monograph/item
Title/Author:
Verification by error modeling/ written by Katarzyna Radecka, Zeljko Zilic.
Reminder of title:
using testing techniques in hardware verification /
Author:
Radecka, Katarzyna.
other author:
Zilic, Zeljko.
Published:
Boston :Kluwer Academic Publishers, : 2003.,
Description:
xiv, 216 p. :ill. ;25 cm.
Series:
Frontiers in electronic testing ;
Subject:
Error analysis (Mathematics) -
Online resource:
https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=118522An electronic book accessible through the World Wide Web; click for information
ISBN:
030648739X (electronic bk.)
Verification by error modeling = using testing techniques in hardware verification /
Radecka, Katarzyna.
Verification by error modeling
using testing techniques in hardware verification /[electronic resource] :written by Katarzyna Radecka, Zeljko Zilic. - Boston :Kluwer Academic Publishers,2003. - xiv, 216 p. :ill. ;25 cm. - Frontiers in electronic testing ;25.
Includes bibliographical references and index.
Electronic reproduction.
Boulder, Colo. :
NetLibrary,
2004.
Available via World Wide Web.
ISBN: 030648739X (electronic bk.)Subjects--Topical Terms:
549972
Error analysis (Mathematics)
Index Terms--Genre/Form:
542853
Electronic books.
LC Class. No.: TK7874.75 / .R33 2003eb
Dewey Class. No.: 621.39/5
Verification by error modeling = using testing techniques in hardware verification /
LDR
:01147cmm a2200265 a 45
001
735006
003
OCoLC
005
20080320
006
m d
007
cr cnu---unuuu
008
250519s2003 maua sb 001 0 eng d
020
$a
030648739X (electronic bk.)
035
$a
ocm56888178
035
$a
735006
040
$a
N
$c
N
$d
OCLCQ
049
$a
AMFA
050
1 4
$a
TK7874.75
$b
.R33 2003eb
082
0 4
$a
621.39/5
$2
22
100
$a
Radecka, Katarzyna.
$3
830954
245
1 0
$a
Verification by error modeling
$h
[electronic resource] :
$b
using testing techniques in hardware verification /
$c
written by Katarzyna Radecka, Zeljko Zilic.
260
$a
Boston :
$c
2003.
$b
Kluwer Academic Publishers,
300
$a
xiv, 216 p. :
$b
ill. ;
$c
25 cm.
440
0
$a
Frontiers in electronic testing ;
$v
25
504
$a
Includes bibliographical references and index.
533
$a
Electronic reproduction.
$b
Boulder, Colo. :
$c
NetLibrary,
$d
2004.
$n
Available via World Wide Web.
$n
Access may be limited to NetLibrary affiliated libraries.
650
$a
Error analysis (Mathematics)
$3
549972
650
$a
Integrated circuits
$x
Verification.
$3
827163
650
$a
Integrated circuits
$x
Very large scale integration
$x
Computer-aided design.
$3
715562
655
$a
Electronic books.
$2
lcsh
$3
542853
700
$a
Zilic, Zeljko.
$3
830953
710
$a
NetLibrary, Inc.
$3
542851
856
4 0
$3
Bibliographic record display
$u
https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=118522
$z
An electronic book accessible through the World Wide Web; click for information
994
$a
92
$b
AMF
based on 0 review(s)
Location:
ALL
電子資源
Year:
Volume Number:
Items
1 records • Pages 1 •
1
Inventory Number
Location Name
Item Class
Material type
Call number
Usage Class
Loan Status
No. of reservations
Opac note
Attachments
W9033620
電子資源
11.線上閱覽_V
電子書
EB
一般使用(Normal)
On shelf
0
1 records • Pages 1 •
1
Multimedia
Reviews
Add a review
and share your thoughts with other readers
Export
pickup library
Processing
...
Change password
Login